Advanced Micro Devices Corporation

Ati Technologies Ulc

Stephen Patrick Thompson

David A Kaplan

Donald W McCauley

Mark Douglas Hummel

Anthony Asaro

David I J Glen

Gordon Caruk

Philip J Rogers

Tarun Nakra

Christopher D Bryant

Gongxian Jeffrey Cheng

Mark A Krom

Gordon F Caruk

The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.

Data cache prefetch hints

A method includes performing a speculative tablewalk. The method includes performing a tablewalk to determine an address translation for a speculative operation and determining whether the speculative operation has been upgraded to a non-speculative operation concurrently with performing the tablewalk. An apparatus is provided that includes a load-store unit to maintain execution operations. The load-store unit includes a tablewalker to perform a tablewalk and includes an input indicative of the operation being speculative or non-speculative as well as a state machine to determine actions performed during the tablewalk based on the input. The apparatus also includes a translation look-aside buffer. Computer readable storage devices for performing the methods and adapting a fabrication facility to manufacture the apparatus are provided.

Speculative tablewalk promotion

The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.

Data cache prefetch throttle

The present application describes a method and apparatus for filtering requests to a translation lookaside buffer (TLB). Some embodiments of the method include receiving, from a first translation lookaside buffer (TLB), an indication of a first virtual address associated with a request to a second TLB for a page table entry in response to a miss in the first TLB. Some embodiments of the method also include filtering the request based on a comparison of the first virtual address and one or more second virtual addresses associated with one or more previous requests to the second TLB.

Filtering requests for a translation lookaside buffer

Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit.

Reading a local memory of a processing unit

The present invention provides a method and apparatus for adapting aggressiveness of a pre-fetcher in a processor-based system. One embodiment includes modifying a rate for pre-fetching data from a memory into one or more caches by comparing a first address of a memory access request to addresses in an address window that includes one or more previously fetched addresses and one or more addresses to be fetched.

Method and apparatus for adapting aggressiveness of a pre-fetcher

A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue. The translation lookaside buffer is adapted for maintaining at least one virtual to physical address translation, and is adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal.

Method and apparatus for controlling a translation lookaside buffer

Instructions involving a relatively significant data transfer or a particular type of data transfer via a cache result in the application of a restricted access policy to control access to one or more partitions of the cache so as to reduce or prevent the overwriting of data that is expected to be subsequently used by the cache or by a processor. A processor or other system component may assert a signal which is utilized to select between one or more access policies and the selected access policy then may be applied to control access to one or more ways of the cache during the data transfer operation associated with the instruction. The access policy typically represents an access restriction to particular cache partitions, such as a restriction to one or more particular cache ways or one or more particular cache lines.

System for restricted cache access during data transfers and method thereof

An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive the status indicator. The memory controller is configured to disable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an active mode. The memory controller further is configured to enable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an idle mode.

CPU mode-based cache allocation for image data

A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each of the plurality of data arrays is selected in response to the cache read request and selecting a first data of the received cache line data from the most recently used way of the cache. An execution of an instruction is stalled if data identified by the cache read request is not present in the cache line data from the most recently used way of the cache. A second data from a most recently used way of one of the plurality of data arrays other than the most recently used data array is selected as comprising data identified by the cache read request. The second data is provided for use during the execution of the instruction.

Growing community of inventors

Longmont, CO, United States of America

Stephen Patrick Thompson