Micron Technology Incorporated

Benhov Gmbh, LLC

Stephen P Van Aken

Robert B Eisenhuth

John L Seabury

Bruce A Liikanen

Gerald L Cadloni

Kenneth James Eldredge

Kenny T Coker

Michael B Danielson

David A Pohm

Larry Joseph Koudele

Guy R Wagner

Bruce A Liikenanen

A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.

Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory

A digital system includes nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of transferring read data and write data relating to the memory, can be changed on a codeword-to-codeword basis based on input parameters.

An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations, An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

Secure subsystem

A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.

Bitwise operations and apparatus in a multi-level system

The present disclosure relates to apparatuses and method for encoding using error protection codes. An example apparatus comprises circuitry, for instance, including an encoder configured to compute parity data based, at least in part, on program data and on predetermined coefficient data. The predetermined coefficient data is determined independent of the program data.

Apparatuses and methods for encoding using error protection codes

An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes at least one module including a nonvolatile memory section that is made up of a plurality of memory devices and the module includes a bit density function to assign a storage density to each memory device such that one group of the memory devices is configured to store data at a high storage density and another group of the memory devices is configured to store data at a low storage density. The module independently performs the bit density function for the nonvolatile memory section of each module based on one or more module input parameters.

Control arrangements and methods for accessing block oriented nonvolatile memory

Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device. Coefficient data representing canonical coefficients can be pre-computed by an apparatus before the apparatus is provided with program data, for example. For example, coefficient data may be pre-computed external to the apparatus and stored before program data is provided to an apparatus.

A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword-to-codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities can be performed.

A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes a plurality of modules, each module including a nonvolatile memory section. In one feature, at least a particular one of the modules is configured to independently maintain a module portion of a distributed flash translation layer for the nonvolatile memory section of only that particular module based on one or more module input parameters. In another feature, a particular module defines an independent execution of at least one of a wear leveling function, a garbage collection function and a bit density function. Associated methods are described.

A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.

Compensation for solid state storage

In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.

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Boulder, CO, United States of America

Stephen P Van Aken