International Business Machines Corporation

Stephen P Thompson

Gary J Morse

Michael Robert Turner

David Carl Frank

Masaki Oie

Thomas Francis Lewis

Sherwood Brannon

Darwin P Rackley

Akihiro Ogura

Kiyoshi Takemura

Hiroshi Satoh

Shigeru Matsubara

William K Shetterly

John J D'Ambrose

Joseph D Harwood

A method and apparatus for increasing efficiency in displaying characters on a display within the data processing system. A plurality of processes for displaying characters on the display in a data processing system are provided. Each of the processes requires a different amount of processor resources to display characters on the display. One of the processes is selected such that the selected process provides a more efficient display of characters on the display than other processes. Characters may be displayed by caching font data in system memory of the data processing system. Glyph bitmaps for a particular character may be moved from the cache to a graphics adapter utilizing a permanent move instruction available in the CPU. Characters are moved to the graphics adapter on a fixed scanline basis, either encompassing the entire width of the character or the entire string of characters on a line.

Method and apparatus for optimizing the display of forms in a data

A full screen of video data is stored in a video memory. A small block of video data to be imminently displayed on a raster scan display device is copied, two double-words (32 bits) at a time, from the video memory to a 6 by 32-bit first in, first out buffer (FIFO). A fill detection circuit determines when the fill level of the FIFO is at or above certain predetermined levels; specifically, 3, 5 and 6 double-words. The current operating mode is stored in a programmable mode register wherein each mode corresponds to a unique screen resolution. For example, one mode corresponds to a 1024 by 768 pixel resolution having 256 colors per pixel, while another mode corresponds to a 320 by 200 pixel resolution having 4 colors per pixel. A minimum fill level is selected by a level selection circuit depending on the current operating mode. Since the FIFO is emptied quickly in a high resolution mode, a higher minimum fill level is selected for high resolution modes than for low resolution modes. Processor access circuitry permits a central processor to write new video data to the video memory. The processor access circuitry, however, is disabled whenever the current fill level is below the minimum fill level set by the level selection circuit. Thus, central processor access to the video memory is only permitted when there is a minimum level of data in the FIFO, and that minimum level of data is selected according to the current operating mode.

Mode dependent minimum FIFO fill level controls processor access to

A system for horizontal expansion of low resolution display modes onto high resolution displays including flat panels at a variable scaling factor is disclosed. The system may be combined with known methods for vertical expansion to allow low resolution display modes to be expanded onto any high resolution display. Two different methods are provided, one for graphics modes and one for text modes, to attain better screen image quality. In the first method, a first pixel data sequence to be expanded is first oversampled at a multiple of the frequency thereof to produce an intermediate oversampled data sequence. The oversampled data sequence is linearly decimated by a factor of less than unity to produce a replicated second data sequence longer than the first, which is then displayed. In the second method, the intermediate oversampled data sequence is filtered to provide an interpolated oversampled data sequence, which is then decimated instead of the intermediate oversampled data sequence, to further improve the screen image quality. No particular mechanism for the graphics controller or display logic is required, eliminating complicated image processing and enabling the size, complexity and cost of the video subsystem of a computer to be reduced.

Horizontal image expansion system for flat panel displays

A method and system for increasing efficiency in the display of characters on a display within a data processing system, wherein the data processing system includes a system memory and a graphics adapter, the system memory having a page mode. A plurality of characters are stored in the system memory as a plurality of glyph bitmaps. Each character has a width, and each glyph bitmap for a character is arranged as a plurality of scanlines such that each of the scanlines includes the width of the character. Selected glyph bitmaps are transmitted from the system memory to the graphics adapter, wherein an occurrence of breaks in the page mode are minimized when the selected glyph bitmaps are moved from the system memory to the graphics adapter, increasing efficiency in displaying characters on a display.

Method and apparatus for optimizing the display of fonts in a data

Method and apparatus for enabling an XGA display adapter selectively to support VGA graphics mode virtualization during native mode operation of the adapter by rendering VGA graphics assist hardware and certain VGA registers accessible. In a preferred embodiment, the invention comprises an XGA display adapter which includes a host interface for interfacing the display adapter with a central processing unit (CPU) of a personal computer (PC), VGA graphics assist hardware for performing VGA graphics assist functions, a memory controller for reading and writing a video memory of the PC as requested by the CPU during video memory accesses, and a display interface for generating control and timing signals to a display of the PC. The XGA display adapter also includes a XGA Operating Mode Register having three control bits which can be written by applications software selectively to enable or disable the virtual VGA function of the present invention. When the virtual VGA function is enabled, logic circuitry within the host interface examines the CPU address associated with each video memory access to determine whether the access comprises a virtual VGA memory access, rather than a native memory access. If so, the host interface routes CPU address and any data to be written to the video memory at that address, which performs the appropriate graphics assist operations on the address and/or data to enable the requested operation accurately to be performed on a virtual VGA memory buffer portion of the video memory by the memory controller.

Display adapter for virtual VGA support in XGA native mode

A method and system for controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least one input/output device having a coprocessor incorporated therein. The system bus electrically connects the system devices. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. Each of the at least one input/output device incorporates control logic therein for (i) monitoring bus activity to calculate the bus mastering time during which the memory controller and the at least one input/output device control the bus, and (ii) outputting an inhibit signal which denies access to the bus by the at least one input/output device if the calculated bus mastering time is equal to or greater than a predetermined bus mastering time period.

System for guaranteed CPU bus access by I/O devices monitoring

A method and system for monitoring and controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least first and second input/output devices each having a coprocessor incorporated therein. The system bus electrically interconnects the system devices and system memory. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. In addition, the memory controller may serve as a bus master on behalf of a slave device requesting access to the system bus. The input/output devices have control logic incorporated therein for (i) determining when an alternate input/output device requests control of the bus, (ii) outputting a preemption signal in response to the alternate request, and (iii) relinquishing control of the bus in response to the preemption signal.

Bus control preemption logic

An interface between a central processing unit (CPU) and a peripheral device is provided which ensures compatibility between existing software for the peripheral device and a CPU of any speed. The interface waveshapes read or write strobe signals in a transfer cycle between the peripheral device and the CPU in order to ensure timing parameters of the peripheral device are not violated by fast CPUs. If the waveshaping causes a change in the timing between first and second consecutive read or write strobe signals, the interface provides a wait signal to the CPU for the purpose of instructing it to extend the transfer cycle of the second strobe signal. In the illustrated embodiment, an interface according to the invention is part of a video interface connecting a microprocessor unit (MPU) and a video digital-to-analog converter (video DAC). Writing or reading color data to or from the video DAC occurs by way of the interface of the invention. The MPU is slowed while it writes or reads color data only when it is required to prevent violation of the timing parameters of the video DAC. In this regard, slower MPUs are not penalized by the invention since wait states are inserted into a transfer cycle only when it is necessary to re-space consecutive read or write strobe signals to prevent the violation of timing parameters.

Apparatus and method for guaranteeing strobe separation timing

A computer adapter card (204) includes a plurality of setup registers (224-226) for receiving setup parameters during initialization of the computer system. Each of the setup registers of an adapter card is accessed at the same address as the corresponding setup register of all other adapter cards in the system. The adapter card is designed to be connected to a computer bus (201) that does not include individual setup lines for each of the adapter cards in the system. To select an individual adapter card, each adapter card includes a register (214) for storing a programmable adapter card number, a plurality of switches (218) for selecting a switch selectable adapter card number, and a comparator (216) for comparing the programmable adapter card number to the switch selectable adapter card number. When an adapter card is initially installed in the computer system, the user sets the switches to correspond to the number of the adapter card slot into which the card is inserted. Thus, the switches of each adapter card in the system are set to a unique switch seleted number. When the comparator detects a match between the programmable and switch selectable adapter card numbers, and when the adapter card is placed in the setup mode, the setup registers (224-226) of the selected adapter card are enabled, such that the computer system can write setup parameters to, and read setup parameters from the setup registers of the selected adapter card.

Computer system with automatic adapter card setup

A hardware-based system for managing multiple input/output devices sharing the same set of addresses in a computer system is described. The new VIRTUAL ENABLED state is a hybrid of the current ENABLED or ACTIVE and DISABLED or INACTIVE states. In the ENABLED state, an input/output (I/O) adapter responds to I/O addressing and presents interrupts to the processor. In the DISABLED state, the I/O adapter does not respond to I/O addressing and does not present interrupts. In the new VIRTUAL ENABLED state, the adapter does not respond to I/O addressing (as in the DISABLED state), but will still produce an interrupt (as in the ENABLED state). With the VIRTUAL state, multiple I/O adapters that would normally content for the same set of addresses (ENABLED state), or optionally be rendered inoperable (DISABLED state), can always remain available for I/O. A single register where the processor can read the interrupt status for all ENABLED and/or VIRTUAL ENABLED adapters sharing the same set of addresses is provided. Other unique registers are also provided to allow the processor to cycle any of the ENABLED and VIRTUAL ENABLED devices between these two states to permit servicing of the interrupt.

Multiple input/output devices having shared address space

Method and apparatus for displaying a horizontal screen separator line between two screen areas. A first step operates a display screen controller (12) in a split screen mode of operation so as to display a first screen area (3) at an upper portion of a display screen (18) and a second screen area (4) at a lower portion of the display screen. The step of operating further includes a step of reading data from a screen memory (42) and displaying rows of corresponding alphanumeric characters. Each character is displayed as a plurality of image pixels arranged along a first number of horizontal scan lines. A further step displays a horizontal visual separator (2) between a last row of the first screen area and a first row of the second screen area. The step of displaying the horizontal visual separator includes the steps of (a) reading data from the screen memory and beginning a display of a row of corresponding visual separator characters; and (b) terminating the display of the row of corresponding visual separator characters after displaying a second number of horizontal scan lines that is less than the first number of horizontal scan lines.

Method and apparatus for displaying a screen separator line

A video subsystem has a CRT (cathode ray tube) display, video controller and video memory for CRT data which requires access by the controller and a CPU (control processing unit). The subsystem monitors activity of the CRT screen display and the video controller and anytime CRT screen display is not required regardless of the time of occurrence, the CPU is allowed to have access to the video memory during the cycle or cycles in which such inactivity of display occurs. A guaranteed minimum number of cycles is assured for access of the video memory by the CPU using a fixed access sequence during the display periods of a high speed mode and shifting to an arbitration strategy to allow CPU access to occur during non-display times of the high speed mode so that the CPU can acquire more cycles to reduce any backlog of requests as necessary. In a low speed mode, the subsystem automatically changes strategy so that arbitration occurs both during display and non-display periods so that the CPU can acquire memory cycles on an as needed basis.

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Delray Beach, FL, United States of America

Stephen P Thompson