Texas Instruments Corporation

Stephen P Sacarisen

Mark A Stambaugh

Michael W Patrick

Gene E Blankenship

Keith W Kawate

William H Giolma

Edward M Gonsalves

Ki S Chang

Damir A Spanjol

Karl M Guttag

Otto N Fanini

David J Myers

Rajiv R Shah

Toan Tran

Johnson J Lin

Steve Thompson

A dual function sensor particularly useful with vehicular coolant systems indicates when a coolant liquid becomes corrosive to such cooling system materials as well as when the liquid falls to a low level condition. A reference and a sense electrode are used to probe the condition of the coolant liquid. Integral electronics provide signal conditioning and transmitting to indicate both corrosive and low level coolant conditions. The sensor assembly mounted directly onto a tubular coupling on the vehicle radiator by pushing the assembly onto the coupling until a spring wire element snaps past a lip formed on the free distal end of the coupling. An electrical connector shroud extends from the assembly and accommodates a mating male connector which is pushed onto the shroud until a clip mounted on the male connector snaps over a locking tab located on the shroud. The male connector typically is connected to an engine control module (ECM).

CMOS/bipolar integrated circuit

A process for making a metal fuse link in a MOS or CMOS process which includes depositing a refractory metal or metal alloy over an already deposited multi-level oxide and patterning the deposited metal or metal alloy so that it has a fusing segment between and integral with expanded segments such that the length and cross sectional area of the fusing segment is sufficiently small so that the fusing current therethrough is less than 20 milliamperes. The fuse and surrounding circuitry is covered with a passivation layer and contacts formed in the passivation layer to the expanded segments.

MOS programmable memories using a metal fuse link and process for making

A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is disclosed. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device therein which operates relatively independently from the host CPU, and which is coupled to the main memory by the system bus, includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data

A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective pairs of input data lines. Each decode circuit has an odd and even output line for providing output signals in response to odd or even number of 1's (or 0's) on an associated pair of row lines, respectively. The circuit includes a precharge discharge circuit coupled to the prestage circuit for generating a first parity signal in response to an odd number of 1's being on the input data lines and a second parity signal in response to an even number of 1's being on the input data lines.

Polyphase parity generator circuit

A dual function sensor particularly useful with vehicular coolant systems indicates when a coolant liquid becomes corrosive to such cooling system materials as well as when the liquid falls to a low level condition. A reference and a sense electrode are used to probe the condition of the coolant liquid. Integral electronics provide signal conditioning and transmitting to indicate both corrosive and low level coolant conditions. The sensor assembly mounts directly onto a tubular coupling on the vehicle radiator by pushing the assembly onto the coupling until a spring wire element snaps past a lip formed on the free distal end of the coupling. An electrical connector shroud extends from the assembly and accommodates a mating male connector which is pushed onto the shroud until a clip mounted on the male connector snaps over a locking tab located on the shroud. The male connector typically is connected to an engine control module (ECM).

Coolant condition sensor apparatus

A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

Microprocessor with integrated CPU, RAM, timer, bus arbiter data for

A microprocessor device is used in an adapter for a communications loop of the closed ring, one-way, token-passing local area network type. Each station has a host processor with a host CPU, a main memory, and a system bus, and has an adapter including the microprocessor tested according to the invention. The adapter coupled to the main memory by the system bus and includes a local CPU (the microprocessor), a local read/write memory, and a local bus. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station receives a free token, the transmit-and-receive controller copies the message frame to be transmitted from the local read/write memory to the outgoing signal path, converting from parallel to serial. When a message addressed to this station is received, the controller converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus. Testing of the microprocessor is accomplished by internal self-test of the registers of the device, using the microcode of the control ROM initiated by a test control input.

Method of internal self-test of microprocessor using microcode

A microprocessor device with an on-chip integrated auto-loaded timer is used in an adapter for a communications loop of the token-passing local area network type. The network has a number of stations coupled to a closed one-way signal path, and each station has a host processor with a host CPU and memory. The microprocessor device with integrated auto-loaded timer is part of an adapter coupled to the host processor. A message frame to be transmitted is copied into a local read/write memory in the adapter by way of the host system bus and a local bus, under initiation by the host CPU. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station has access to the loop (i.e., receives a free token) the transmit-and-receive controller copies the message frame from the local read/write memory to the outgoing signal path, converting from parallel to serial. When the transmit-and-receive controller receives a message addressed to this station, it converts it from serial to parallel, and copies the message frame into the local read/write memory via the local bus, interrupting the local CPU. The message frame is then copied from the local read/write memory to the main memory.

Microprocessor device with integrated auto-loaded timer

A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. Each instruction is executed in a sequence of microstates which are generated by selecting an entry point for the first address in a control ROM then continuing with a series of jumps and/or further entry points determined by the instruction and by the current state of the microprocessor. Improved circuitry is provided for selecting the entry point using a minimum of space on the chip by detecting the position of the leading 1 bit. Thus an instruction set can be used in which different groups of instructions have different numbers of leading zero bits.

Growing community of inventors

Houston, TX, United States of America

Stephen P Sacarisen