Semiconductor Components Industries, LLC

Motorola Corporation

Other

Stephen P Robb

Francine Y Robb

Alan Richard Ball

Zheng Shen

Lewis E Terry

David M Heminger

John P Phipps

Paul J Groenig

Prasad Venkatraman

Zia Hossain

Jeffrey Pearse

Floyd E Anderson

Judith L Sutor

David K Briggs

Pern Shaw

Gary V Fay

Robert E Rutter

Judy L Sutor

Michael D Gadberry

Alejandro Lara-Ascorra

John M Pigott

David M Susak

Paul W Sanders

Dennis L Welty

Kim Roger Gauen

John R Qualich

Scott L Craft

John Bliss

William L Fragale

Lloyd H Hayes

Suzanne Nee

Chang Su Mitter

Li-Hsin Chang

Jean-Michel Reynes

Robert F Hightower

Margaret E Fuchs

In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

Method of forming an integrated power device and structure

In one embodiment, a semiconductor device to provide protection for electronic circuits, the semiconductor device typically includes a vertical MOS transistor, a reference circuit, and an amplifier. The amplifier amplifies the reference voltage to enable the vertical MOS transistor responsively to a transient event.

Transient suppression device and method therefor

In one embodiment, and electro-static discharge detector is formed with a plurality of channels and is configured to detect a positive electro-static discharge and a negative electro-static discharge.

Method of forming an ESD detector and structure therefor

In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.

Method of forming a bi-directional transistor with by-pass path

A method and circuit for managing thermal performance of an integrated circuit. Temperature sensing circuits and a plurality of power FETs that are coupled together in parallel are manufactured from a semiconductor substrate. Each temperature sensing circuit monitors the temperature of the portion of the semiconductor substrate near or including a corresponding power FET. When the temperature of the semiconductor substrate near one or more of the power FETs reaches a predetermined value, the corresponding temperature sensing circuit reduces a voltage appearing on the gate of the power FET. The reduced voltage increases the on-resistance of the power FET and channels a portion of its current to others of the plurality of power FETs. The power FET continues operating but with a reduced current flow. When the temperature of the semiconductor substrate falls below the predetermined value, the gate voltage of the power FET is increased to its nominal value.

Method for regulating temperature

Bi-directional transistor with by-pass path and method therefor

In one embodiment, an LED control circuit is configured control a current through an LED responsively to a value that is proportional to a control signal for values of the control signal that are less than a threshold value of the control signal and to control the current to a value that is proportional to the threshold value for values of the control signal that are greater than the threshold value.

LED control circuit and method therefor

In one embodiment, a vertical N-channel transistor is coupled in a high side configuration to control a current through an LED. A control circuit operates the vertical N-channel transistor to control a value of the current.

LED controller and method therefor

In one embodiment, a protection device is used to protect a circuit. The protection device has a maximum rated power dissipation that is less than a maximum rated power dissipation of the circuit that is being protected.

Shunt protection circuit and method therefor

Method for regulating temperature and circuit therefor

In one embodiment, an in-rush limiter is configured to control an output voltage to increase at a rate that is independent of the load that is powered by the in-rush limiter.

Method of forming an in-rush limiter and structure therefor

Growing community of inventors

Tempe, AZ, United States of America

Stephen P Robb