Texas Instruments Corporation

Stephen P Hamilton

Michael J Cochran

Arthur C Hunter

Larry L Miles

Kenneth A Lies

Charles P Grant, Jr, Deceased

Larry D Propst

Richard D Harris

Thomas E Merrow

Harry G McFarland

Lee G Kitchens

John W Richardson

Robert R Kressler

Robert E Belland

Johnny M Barrett

Bruce E Aldridge

This addressing system, advantageously for smaller scale data processors with relatively narrow data paths, facilitates transferring pluralities of multibit data words, e.g., storing or fetching the contents of a multidigit register in a calculator. A bidirectional bus couples a controller and a plug-in memory. The controller generates address, data, and command signals. A decoder receives command signals and outputs signals to a program counter (PC) alternatively indicating a normal mode, in which the controller accesses a single specified memory address, or a multiple access mode, in which a predetermined number of sequential addresses are accessed starting at a specified address. In response to selective command decoder output, the PC alternatively may store received addresses, output stored count values to the controller or to a memory array, or increment the count value in synchronism with data transfers to/from multiple memory locations. The decoder, PC, and memory array are contained within the portable memory module's housing, which may be mounted in another housing containing the controller. In a ROM embodiment, the mounted memory is powered directly from a source in the controller housing. In a RAM embodiment, the module's housing includes a power switching circuit and an internal battery to provide uninterrupted power to the read/write memory cells irrespective of whether the module is mounted or detached.

Memory system with single command selective sequential accessing of

Disclosed is a non-volatile memory system which includes a first power means for providing a main power source; a read/write memory means for storing and retrieving data signals so long as power is provided; and second power means for coupling to the first power means and to the read/write memory means, the second power means including auxiliary power means for providing a second power source; the second power means further including controller means for continuously providing power to the read/write memory means from either the first power means or the auxiliary power means. In the preferred embodiment, the first power means is within a housing, said housing having a compartment for the receipt of a plug-in module, and the second power means and read/write memory means are contained within the plug-in module. Additionally, in the preferred embodiment, the memory means and the second power means exclusive of the second power source are comprised of a single integrated circuit. Furthermore, in the preferred embodiment, the power controller and memory system are coupled to a data processing system such as an electronic calculator.

Non-volatile memory system

A data processing system having separate read-only memory and read-write memory integrated circuits coupled to a central processing unit via the same interface system. The data processing system is comprised of bus means having either command, address, or data signals present and conducted thereon. In the preferred embodiment, the bus means is comprised of a four binary digit bidirectional conductor bus coupling between the central processing circuit and the memory circuits. In the preferred embodiment, the data processing system is further comprised of processor means within said central processing unit coupled to the bus means for selectively transmitting selected ones of said command, data and address signals onto the bus means, said processor means further including means for receiving certain other ones of said data and address signals from the bus means; and memory means including, in the preferred embodiment, read-only memory circuits and read write memory circuits, coupled to the bus means (and to the processor means via the bus means), including means for selectively transferring data with the processor means in response to said received command and address signals being within a unique subset of commands and addresses. In the preferred embodiment, each separate individual circuit comprising the memory means includes the means for responding to the command signal received via the bus means and for storing or outputting address signals or data signals responsive to decoding said received command signal.

Memory system having a common interface

A memory interface system employs a communications protocol to distinguish between command signals, address signals and data signals appearing on the same bus lines. Each memory coupled to the bus lines detects the change between a default state on the bus lines and a command signal. A detector within each memory determines from the received command signal the type of memory operation to be performed and prepares the memory for that operation. These operations may include reading or writing data within specified locations in the memory or reading or writing within the program counter associated with the memory. The detector is only responsive to received command signals when a predetermined state follows the default state.

Memory interface system having combined command, address and data buss

A memory system includes a multiple memory pointer in which a pointer selection signal selects one of a plurality of memory pointers to generate an address signal for application to the memory for controlling the location of memory operations. In the preferred embodiment the memory is arranged in an X by Y matrix having X times Y individually addressable memory locations. A first pointer circuit has a plurality of address pointers, one of which is selected for generation of an X coordinate address. A second pointer circuit includes a single address pointer for generation of the Y coordinate address. The second pointer circuit may be a multiple pointer in an alternative embodiment. By provision of a number of individually addressable memories responsive to the same memory pointer system, separate application of address signals from differing address pointers to differing memories permits multiple memory operations in a single instruction cycle.

Multiple pointer memory system

A thermal printer system for actuating a plurality of groups of thermal printing elements. The system includes a first circuit in which a plurality of data words are stored, the words representing the characters to be printed. A second circuit converts the data words into printing character codes. A selected bit from each code, which bit is sequentially altered, is supplied to a third circuit for actuating the printing elements.

Thermal line printer

An alphanumeric display system which may be implemented on one or more semiconductor chips for controlling display devices arrayed in N groups, each group of which comprises an A by B matrix of devices and which is capable of displaying a single alphanumeric character. The display devices in each group are sequentially addressed with display commands being communicated therewith in a predetermined manner to cause the display devices to visually display a predetermined alphanumeric character. Use of the alphanumeric display system herein disclosed, permits a total of A by B by N display devices to be controlled by the display system using as few as A + B + N connecting conductors to control the display devices and associated display driver devices.

Alphanumeric display system

An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having a arithmetic unit and memory system. The arithmetic unit and memory system include a plurality of operational registers and an arithmetic unit having two inputs and an output. A plurality of operational registers selector gates interconnect the operational registers and arithmetic unit for connecting any selected two of the plurality of operational registers to the inputs of the arithmetic unit. The plurality of operation register selector gates preferably comprise individual MOS transfer gates.

Electronic calculator or microprocessor having a multi-input arithmetic

An electronic calculator or microprocessor system of a type preferably having keyboard input and the visual display is implemented with a semiconductor chip having an arithmetic unit, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable in response to the address stored in the address register and an, instruction word decoder circuit for decoding instruction words outputted from the instruction word memory and for controlling the arithmetic unit in response thereto. An indirect addressing system includes an auxiliary register coupled to the output of the arithmetic unit for storing at least a portion of a word of numeric data outputted by the arithmetic unit and a branch logic system responsive to the decoding of a particular instruction word by the instruction word decoder logic for causing the address register to branch to a location defined by the contents of the auxiliary register.

Electronic calculator or microprocessor with indirect addressing

An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having an arithmetic unit, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable by the address register, and instruction word decoder logic for decoding the instruction words and for controlling the arithmetic unit in response thereto. The system further preferably includes a plurality of operational registers for storing numeric data received from the input or outputted by the arithmetic unit and a plurality of operational register selector gates coupling the operational registers with the arithmetic unit or with each other. The instruction word decoder logic includes mask logic for generating mask signals to the plurality of operational register selector gates. Thus the instruction word decoder logic decodes instructions for operating selected ones of the plurality of operational registers to effect arithmetic operations by coupling selected operational registers to the arithmetic unit or data exchange operations by coupling selected operational registers together. The mask logic also controls the selected operational registers for determining what portions of the words of numeric data stored in the operational registers are to be operated on arithmetically by the arithmetic unit or to be exchanged during data exchange operations.

Electronic calculator or microprocessor with mask logic effective during

This invention relates to enhancement of calculator versatility through connections provided in a calculator cradle leading to a printing mechanism therein when a calculator is nested in the cradle. In a more specific aspect, the invention relates to the communication between a calculator and a printer module which nests the calculator and responds to instructions and data flow from the calculator to print selected calculator information.

Calculator-print cradle system

A thermal line printer includes a semiconductor chip for control of A .times. N heaters arrayed in N groups past which thermally sensitive paper is stepped B times in printing a line of characters in an A .times. B dot matrix. A sequential access memory stores N multibit words, one word for each character to be printed on a given line with a commutator cyclically to read words from the memory A .times. B times for each line to be printed. A ROM has an A .times. B dot matrix code therein for each available character. A time sequencer and decoder connected to the ROM is synchronized with the commutator to produce a different one bit output from the ROM each time each given word is read from memory. A set of N enable circuits leads from the ROM to N groups of heaters. A set of A enable circuits leads from the sequencer to A groups of heaters where one heater in each A group is from one of the N groups. A decoder interfaces the sequencer to the A groups of heaters and to the motor sequentially to enable the heaters in one A group for each memory cycle and in order through the A columns and B rows of the matrix.

An error correction system is particularly suitable for user programmable calculators which may be programmed to perform a series of functions on data entries by means of a series of program steps entered into the calculator from a storage media such as recorded magnetic cards or the like. Data is stored in one or more pairs of tracks on the recording media with the first track of each pair for storing binary zeros and a second track of each pair for storing binary ones. Each time a binary zero is present, an alternating transition negative to positive or positive to negative appears on the zero's track of the storage media and each time a one is present an alternating transition negative to positive or positive to negative appears on the one's track of the storage media. For reading the data stored on the storage media, means such as a data latch is provided for each track for storing the direction of the previous transition positive to negative or negative to positive for that track and means for comparing the direction of such previous transition with the direction of the present transition. Whenever it is determined that the state of a bit of data is missing on a pair of tracks, i.e., no transition stored on either track for a given bit, the transitions located prior to, and following said missing bit will indicate the track on which the data bit should have been stored and hence the state of the missing bit. In an embodiment in which at least two pairs of tracks are utilized, the ORed output from the first pair of tracks may be compared to the ORed output from the second pair of tracks such that whenever a bit appears for the first pair but not the second pair it is determined that a bit is missing for the second pair.

Error correction system in a programmable calculator

A method of assembling, positioning, and making connections to a thermal printhead is disclosed. A substrate is provided upon which heating elements or mesas are mounted. Leads from these heating elements are continued on the same side of the substrate as the one on which the elements are located. The leads are brought to terminal pads where connections may be made to the logic circuit which selectively energizes the heating elements to form numerals or characters on heat sensitive paper. A flat flexible cable with conductor ends exposed is held in place so that the exposed conductor ends make contact with the terminal pads of one or more of such substrates. The substrates and cable are clamped together by two metal plates. This entire assembly is mounted on a spring-loaded pivot arrangement so as to hold the heating elements against the heat sensitive paper on an advancing platen. Connections may be made between the cable conductors and the printing logic to allow the heating elements to be energized.

Growing community of inventors

Garland, TX, United States of America

Stephen P Hamilton