Leland Stanford Junior University

Arraycomm, Inc.

Barcelona Design, Inc.

Tokyo Electron Limited

Verizon Patent and Licensing Inc.

Carnegie Mellon University

Globalstar, Inc.

Strider Labs, Inc.

Sabio Labs, Inc.

Helios Photonics, Inc.

Stephen P Boyd

Christopher Richard Uhlik

Marc H Goldburg

Craig H Barratt

David M Parish

Louis C Yun

Maria Del Mar Hershenson

Mar Hershenson

Arash Hassibi

Lieven Vandenberghe

Deepak Kakadia

Thomas H Lee

Yang Xu

Abbas A El Gamal

Andrea Caprara

Sunil C Shah

Lawrence Thomas Pileggi

Mark Alan Erickson

Ioannis Kanellakopoulos

Eliot Leonard Wegbreit

Richard H Sherman

Sunderarajan Sunderesan Mohan

Andre Hentz

Delmer R Schneider, Jr

Hai Shao

Xiling Shen

Yong Gao

Sunderarjan Mohan

Dave Colleran

Cesar Crusius

Lungying Fong

Derek U Gerlach

A device may receive performance information for a traffic flow assigned to a quality of service (QoS) class. The device may determine an overall packet delay, associated with the traffic flow, based on the performance information. The device may determine a radio access network (RAN) delay, associated with the traffic flow, based on the performance information. The device may determine a target packet delay associated with the QoS class. The device may identify, based on the target packet delay, the RAN delay, and the overall packet delay, a QoS sub-class to which the traffic flow is to be assigned. The QoS sub-class may be associated with the QoS class. The device may cause packets, associated with the traffic flow, to be marked for treatment in accordance with the QoS sub-class.

Optimized quality of service transport architecture to compensate for SINR variations

A method for rapidly determining feasibility of a force optimization problem and for rapidly solving a feasible force optimization problem is disclosed. The method comprises formulating the force optimization problem or force feasibility problem as a convex optimization problem, formulating a primal barrier subproblem associated with the convex optimization problem, and solving the primal barrier subproblem. The method and related methods may also be used to solve each problem in a set of force optimization problems, determine the minimum or maximum force required to satisfy any of a set of force optimization problems, solve a force closure problem, compute a conservative contact force vector, or solve a feasible force optimization problem with bidirectional forces.

Method for fast computation of optimal contact forces

Optimization design method for configurable analog circuits and devices resulting from same. An implementation fabric for a given application domain can be accurately pre-characterized in terms of devices and parasitics. Customization structures are designed and characterized to be applied to the fabric to customize a device for a particular application. In some embodiments, characterization is accomplished by formulating a configurable design problem as an optimization with recourse problem, for example, a geometric programming with recourse (GPR) problem. Devices can be produced for multiple applications from the application domain using the same optimized fabric to provide predictable performance.

Optimization and design method for configurable analog circuits and devices

This invention relates to a method and apparatus for transmitting a downlink signal from a communication station to one or more subscriber units to achieve a desired radiation level over a desired sector (e.g., everywhere), the communication station including an array of antenna elements and one or more signal processors programmed (in the case of programmable signal processors) to weight the downlink signal according to one of a sequence of complex valued weight vectors. The method includes sequentially repeating transmitting the downlink signal, each repetition with a different weight vector from the sequence until all weight vectors in the sequence have been transmitted with. The sequence is designed for achieving the desired radiation level during at least one of the repetitions. In this way, every user in the desired region is transmitted to in the time period.

Downlink broadcasting by sequential transmissions from a communication station having an antenna array

A method and apparatus for parsing signomial and geometric programs, referred to herein as 'the Parser'. Signomial and Geometric programming is a unique class of mathematical problems that is useful in the study of optimization problems. The Parser is a program designed to recognize and parse both signomial and geometric programs such that they may be accepted and solved by signomial and geometric program solvers. The Parser accepts an optimization problem from a user in the form of algebraic expressions. The Parser can then identify the problem as a signomial program and can further determine if it reduces to a geometric program. If either a signomial or geometric program exists, the Parser converts the algebraic expressions to a compact numeric format that can be accepted by a computer-aided solver. In the case of a geometric program, the solver may find a global solution to the optimization problem. However, in the case of signomial program, the solver may only find a local solution. The solution found by the solver is routed back to the Parser which reports it in a user-readable format.

Parser for signomial and geometric programs

A method is described for optimal simultaneous design and floorplanning of integrated circuits. The method is based on formulating the problem as a geometric program, which then can be solved numerically with great efficiency. Prior work discloses the design of many different analog circuit cells such as operational amplifiers, spiral inductors, and LC oscillators which can be cast as geometric programs. The present disclosure adds to this layout floorplanning constraints in posynomial form that can be mixed with design constraints for different analog circuits. This allows the simultaneous design and floorplanning of numerous analog circuits using geometric programming. Thus, the design and floorplanning can be performed optimally in a single step.

Optimal simultaneous design and floorplanning of integrated circuit

In one embodiment, the invention is a method. The method is a method of routing a circuit having a set of nets and a set of circuit elements specified as a slicing tree and a set of linear constraints. The method includes finding short paths for the set of nets based on a minimum-spanning-tree solution to a floorplan derived from the slicing tree for each net of the set of nets. The method also includes routing the nets as conductors within channels of the floorplan, the conductors having locations satisfying a set of linear constraints based on the solution of a linear optimization problem.

Method and apparatus for routing an integrated circuit

A generalized tunable optical filter with interconnected processing devices, such as unequal arm Mach-Zehnder interferometric devices and ring resonator devices, is described. Each of the processing elements is characterized by a parametric length &#x394;l=n&#x394;lwhere nis an integer greater than 30 and &#x394;lis the longest length common to all of the processing elements. The optical filter is tuned by the setting of actuators in the processing elements with each setting corresponding to a predetermined filter response, such as for chromatic dispersion compensation and WDM add/drop multiplexer applications. To determine the design variables of the optical filter, such as the coupling angles &#x3b8; and parametric lengths &#x394;lfor the processing elements, a methodology of determining these variables from the desired application is also described.

Tunable optical waveguide filters with optimized lengths and method of designing same

A method and system for joint spindle speed and head position control in rotating media storage systems are described. A controller changes the rotation speed of a spindle assembly based upon the position information of a desired data sector. This controller may also control the actuator assembly based upon the position information of the desired data sector.

Joint spindle speed and head position control in rotating media storage systems

A method for the design and optimization of inductors for RF circuits. This method consists in the formulation of RF circuit designs as geometric programs. The designer can specify a wide variety of specifications such as gain, bandwidth, noise, etc. The method, which was implemented in simple code, determines inductor dimensions and component values in a few seconds real-time. The results was also a globally optimal design.

Optimal design of an inductor and inductor circuit

A method for optimizing an integrated circuit uses a dominant time constant of a transition of the circuit. A physical layout of the circuit is characterized in terms of design parameters. The circuit is modeled by a conductance matrix G and a capacitance matrix C, wherein G and C are affine functions of the design parameters. The optimization method comprises the step of finding the values of the design parameters that optimize a property of the circuit while simultaneously enforcing a constraint that the dominant time constant must be less than a maximum value t,. Mathematically, the constraint on the dominant time constant can be written: t,G&minus;C&gE;0. The optimization method can be used when the circuit has a non-tree topology. Furthermore, when the design parameters comprise variables that relate to sizes of elements of the circuit, a topology of the circuit is optimized by the optimization method. In some embodiments the circuit is optimized for a plurality of transitions, and in some embodiments the design parameters are subject to design constraints.

Optimization of integrated circuit properties through constraints using a dominant time constant

A system for designing and optimizing integrated circuits. Design objectives and constraints are described as posynomial functions of the design parameters. The circuit design problem is then expressed as a special form of optimization problem called geometric programming, to which very efficient global optimization methods are applied. The present invention can thereby efficiently determine globally optimal circuit designs, or globally optimal trade-offs among competing performance measures such as, for example for an operational amplifier (op-amp), power, open-loop gain, and bandwidth. The present invention therefore yields automated synthesis of globally optimal circuit designs for a given circuit topology library, directly from specifications.

System and method for designing integrated circuits

Method for sequentially transmitting a downlink signal from a communication station that has an antenna array to achieve an omnidirectional radiation

A satellite communications system operative with at least one existing terrestrial communication system for carrying traffic is described. The communication system has a plurality of satellites in earth orbits, each satellite including a battery for sourcing electrical energy. The battery has energy sourcing limits. Gateways, bidirectionally linked to the plurality of satellites are also provided. A computing center, linked to the gateways, has a traffic control means for allocating traffic to the gateways. The traffic control means has three parts a power demand model for computing a first traffic allocation of traffic for each satellite; a satellite battery performance model descriptive of the energy sourcing limits of the on-board batteries; and a control law for applying weights to the first traffic allocation by using the battery performance model to obtain a second traffic allocation for each satellite. The second traffic allocation induces an electrical energy consumption in each of the satellites that is less than the battery energy sourcing limits.

Dynamic traffic allocation for power control in multiple satellite

Growing community of inventors

Stanford, CA, United States of America

Stephen P Boyd