Dallas Semiconductor Corporation

Maxim Integrated Products, Inc.

Dallas Semiconducter Corp.

Stephen N Grider

Wendell L Little

Joseph Wayne Triece

Edward Tangkwai Ma

Bradley M Harrington

Andreas Curiger

James E Bartling

David A Bunsey

Edward Tang Kwai Ma

Shyun Liu

Frank V Taylor, Iii

Michael L Bolan

Stephen M Curry

Matthew K Adams

Don Folkes

Joseph P Gorski

Andrew D Jones

Ann Little, Legal Representative

Ann Little

Methods, systems, and arrangements enable increased security for a processor, including by implementing block encryption. The block may include multiple instructions and/or operations to be executed by the processor. The block may also include multiple bytes that are read into the processor byte by byte. Once a block-wide encrypted buffer has been filled from an external memory source, the block may be decrypted using an encryption algorithm (e.g., the Data Encryption Standard (DES), the triple DES, etc.), and the decrypted block may be forwarded to a decrypted buffer. The decrypted block may thereafter be moved into a cache, which may optionally be organized into an equivalent block width (e.g., for each way of a multi-way cache). Therefore, when a processing core/instruction decoder needs a new instruction, it may retrieve one from the cache, directly from the decrypted buffer, or from external memory (e.g., after undergoing decryption).

Encryption-based security protection for processors

A secure microcontroller system comprising an integrated cache sub-system, crypto-engine, buffer sub-system and external memory is described according to various embodiments of the invention. The secure microcontroller incorporates block encryption methods to ensure that content communicated between the integrated microcontroller and external memory is protected and real-time performance of the system is maintained. Additionally, the microcontroller system provides a user-configurable memory write policy in which memory write protocols may be selected to balance data coherency and system performance.

Block encryption security for integrated microcontroller and external memory system

Methods, systems, and arrangements enable efficient reprogramming of a memory block of a microcontroller. Two blocks of memory each have a different logical location with respect to a processor of the microcontroller. The first memory may store vector information to be executed by the processor. The second memory may store data information. The logical location of each memory block is dependent on the value of a pre-determined bit in a specified register. When a user wishes to reprogram the contents of the first memory, the user enters new code into the second memory. Upon completion, the value of the pre-determined bit is changed, and the logical locations of the first and second memories are interchanged. In effect, the newly entered code from the second memory is accessed as if it were in the first memory (e.g., from an addressing perspective), and the processor may execute the new program (e.g., after the processor undergoes a system reset).

Memory exchange

The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX ) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.

Method and apparatus for 24-bit memory addressing in microcontrollers

An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.

Parasitically powered microprocessor capable of transmitting data over a single data line and ground

Microprocessor with coprocessing capabilities for secure transactions and quick clearing capabilities

An improved clocking system for micro controllers is provided. The micro controller has two mechanisms by which the clocking is provided. One clock is provided by an external clock signal which is generally crystal controlled. A second mechanism for providing the clock is also present. This second clock can be useful as the 'primary' or first clock which is generally a crystal oscillator may take several milliseconds to stabilize following a restart from a stop mode. The second clock mechanism can for example be an internal ring oscillator or other type of clock which although not as accurate as a crystal clock does not require the several milliseconds to recover.

Clocking system for microcontrollers

A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.

Microcontroller having register direct and register indirect addressing

An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.

Secure module with microprocessor and co-processor

A nonvolatile microcontroller (or microprocessor) with improved security against tampering, including attempts at active intrusion. According to this invention, a battery-backed microcontroller includes encryption and power management functions, and is combined with a battery and a volatile semiconductor memory (e.g. an SRAM). The microcontroller supplies power to the semiconductor memory (either from a system power supply or from the battery). When a security violation is detected, the microcontroller wipes its encryption registers, and also grounds the power-output pin to the memory. This will destroy all data in the volatile memory.

Microprocessor with single pin for memory wipe

Microprocessor output driver

Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR. The circuitry also comprises a mask register having a plurality of mask register inputs and a plurality of mask register outputs, the plurality of mask register inputs connected to the plurality of interrupt inputs and the plurality of mask register outputs connected to the plurality of combinatorial logic inputs wherein a mask register bit pattern in the mask register conditions a corresponding subset (possibly empty) of the interrupt signals at the plurality of interrupt inputs to make the function and the interrupt output signal at the interrupt output not depend upon the corresponding subset.

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Argyle, TX, United States of America

Stephen N Grider