The Solartron Electronic Group Limited

Stephen N Cope

A microprocessor is programmed to perform the DFT on data points read out from and written back into a RAM. In each of a plurality of levels of the transform the points are read out in small groups, subjected to a discrete Fourier transform and written back into different addresses in order to avoid jumbling the order of the points in the ultimate output. The read-out and write-in addresses are read out of a PROM in sequence for each group and added to a base address in a latch. A -N latch, adder and multiplexer ensure that the addition is modulo N. After each group, the base address is changed to a new value by adding another value read out of the PROM and all addresses are worked through in this way in each level. At the start of each level the microprocessor puts the correct PROM start address in a latch and the number of groups (m) in a counter which is decremented to count off the groups and signal the end of a level. The PROM thus stores address value sequences for each level, starting at different start addresses. Moreover there may be different sets of start addresses for different algorithms catering for different numbers of points and forward and inverse transforms.

Discrete Fourier transform with non-tumbled output

The invention enables a logarithmic plot to be generated for values pertaining to uniformly spaced sampling points of a frequency axis, for example, such as the values provided by a discrete Fourier transform processor, while utilizing a conventional display device with a linear time base. To this end the array of input values provided by the processor is converted in a further processor to values corresponding to points uniformly spaced along a logarithmic frequency axis. If points on the logarithmic and linear axis are indexed by values x and y respectively, the y values (in general non integral) corresponding to x-1/2 and x+1/2 are calculated, the corresponding integral values of y are ascertained and the output value corresponding to x is formed as a weighted sum of the input values for these two integral y values and any intervening integral y values. The display is obtained by addressing the output values synchronously with the time base through an address circuit 17 and converting the values in a digital to analog converter 14 before application to the Y input of the display device 15.

Growing community of inventors

Farnborough, United Kingdom

Stephen N Cope