Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Other

Stephen Morley

Kenneth Kay Smith

Stewart R Wyatt

Jonathan Jedwab

James Andrew Davis

Kenneth Graham Paterson

Frederick A Perner

Mark Robert Watkins

Toshiyuki Hirose

Nigel Kevin Rushton

Dominic Paul McCarthy

Kevin Lloyd-Jones

Robert Alan Williams

Peter Joseph Bramhall

Shinya Osaki

A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the MRAN device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data, using either a parametric evaluation (step), or a logical evaluation (step) or preferably a combination of both. Failed cells are identified and a count is formed, suitably in terms of ECC symbolsthat would be affected by such failed cells (step). The count can be compared to a threshold (step) to determine suitability of the accessed storage cells and a decision made (step) on whether to continue with use of those cells, or whether to take remedial action.

Manufacturing test for a fault tolerant magnetoresistive solid-state storage device

A magnetoresistive solid-state storage device (MRAM device) uses storage cellsarranged in many arraysto form a macro-arrayFor fast access times and to reduce exposure to physical failures, each unit of data (e.g. a sector) is stored with a few sub-units (e.g. bytes) in each of a large plurality of the arraysAdvantageously, the plurality of arraysare accessible in parallel substantially simultaneously, and a failure in any one array affects only a small portion of the data unit. Optionally, error correction coding (ECC) is employed to form encoded data with symbols which are stored according to preferred embodiments which further minimise exposure to physical failures.

Magnetoresistive solid-state storage device and data storage methods for use therewith

Systems and methods for controlling communication with nonvolatile memory devices via a memory bus are provided. Briefly described, one of many possible embodiments is a system comprising a memory controller in communication with a memory bus, the memory controller configured to control communication with at least one nonvolatile memory device by configuring the at least one nonvolatile memory device, via the memory bus, with a unique device identifier.

Systems and methods for controlling communication with nonvolatile memory devices

In a digital data storage system providing two or more levels of interleaved Reed-Solomon error correction coding together with a track checksum, the track checksum is calculated according to an algorithm which has no correlation with the Reed-Solomon codeword generation rules. This allows miscorrections at the C correction level to be determined reliably thereby enhancing the correction rate. Also disclosed is a system which uses the enhanced ability to identify C miscorrections, to mark C miscorrections to the third level of error correction thereby allowing double error correct at the third level.

Methods and apparatus for data storage on magnetic media including error correction codes

A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of '1's and '0's, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the &lsquo;1&rsquo;s and &lsquo;0&rsquo;s are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.

Data balancing scheme in solid state storage devices

A method for correcting errors when writing a stream of data to a data, received from a host apparatus, to a magnetic tape data storage medium comprises: partitioning the stream of digital data into a plurality of fragments; writing the plurality of fragments to the data storage medium; reading the plurality of fragments from the data storage medium; checking whether each of the read fragments are correct; assigning each of the correct read fragments to only one of a plurality of groups of fragments; counting a total number of correct read fragments within each of the plurality of groups of fragments; and if the total number of correct read fragments within any of the plurality of groups of fragments is less than the threshold number of correct read fragments then the step of writing the plurality of fragments to the data storage medium is repeated.

Data writing to data storage medium

The present invention concerns a multiplexer for use in a system for transmitting more than one type of data, e.g. a system for transmitting voice and data. The invention eliminates transmission errors in framed data due to clock errors on the transmission side by appropriate choice of the length of multiplexer frames. Two embodiments are disclosed, one in which the frame rate of the multiplexer is greater than the frame rate of a voice coder and another in which the length of multiplexer frames is slightly adjustable to account for clock errors.

Growing community of inventors

Bristol, United Kingdom

Stephen Morley