Intel Corporation

Agere Systems Inc.

Stephen Miller

Narender R Vangati

Tsung-Yuan Charles Tai

Ren Wang

Andrew J Herdrich

Debra Bernstein

Jr-Shian Tsai

David Sonnier

Stephen R Van Doren

William G Burroughs

Niall D McDonnell

Hugh Wilkinson

Yipeng Wang

Andrew Cunningham

Bruce Richardson

James T Clee

Jerry Pirog

Joseph R Hasting

Gage Eads

Jonathan Kenny

Te Khac Ma

Jamison D Whitesell

An Yan

Edwin Verplanke

Bradley A Burres

Namakkal N Venkatesan

Abraham Prasad

Prachi Kale

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

Technologies for a distributed hardware queue manager

Techniques are disclosed for generating a representation of an access control list, the representation being utilizable in a network processor or other type of processor to perform packet filtering or other type of access control list based function. A plurality of rules of the access control list are determined, each of at least a subset of the rules having a plurality of fields and a corresponding action. The rules are processed to generate a multi-level tree representation of the access control list, in which each of one or more of the levels of the tree representation is associated with a corresponding one of the fields. At least one level of the tree representation comprises a plurality of nodes, with two or more of the nodes of that level having a common subtree, and the tree representation including only a single copy of that subtree. The tree representation is characterizable as a directed graph in which each of the two nodes having the common subtree points to the single copy of the common subtree.

Directed graph approach for constructing a tree representation of an access control list

A processing system includes a processing device and a host processor operatively coupled to the processing device via a system bus, and implements a scatter gather data transfer technique. The host processor is configurable to control the transfer of information to or from scattered or non-contiguous memory locations in a memory associated with the processing device, utilizing a data structure comprising a single descriptor. An information transfer bandwidth of the system bus is thereby more efficiently utilized than if a separate descriptor were used for transfer of information involving each of the non-contiguous memory locations.

Single descriptor scatter gather data transfer to or from a host processor

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Round Rock, TX, United States of America

Stephen Miller