At&t Bell Laboratories

Bell Telephone Laboratories

Stephen M Walters

Robert L Farah

Guido Bertocci

A bit compression multiplexer (FIG. 2) for a pair of time division multiplexed digital bit streams each one of which includes a plurality of PCM encoded signals deposited in separate and distinct channels of a repetitive frame and signaling bits multiplexed therewith. The PCM encoded signals of successive frames are normally bit compressed (23) into n-bit signals, but periodically the encoded signals of a frame are bit compressed into n-1 bit signals. The bit compressed signals of the pair of bit streams are time division multiplexed (24) with each other, with the multiplexed compressed signals occupying separate and distinct channels of a repetitive frame. The signaling bits are extracted (21) from the pair of digital bit streams and are inserted (24) into predetermined n-1 bit channels of the last-recited repetitive frame. The signaling bits that are placed in a given channel are related to the encoded message signal of that channel.

Bit compression multiplexer

A bit compression coding circuit incorporates signaling bit insertion. An input signal sample(s) representing, for example, PCM encoded speech or voiceband data, is delivered to a difference circuit (31) where a predicted signal (s.sub.e) is subtracted from it. The predicted signal is an estimate of the input sample derived from a predictor (32). The resultant difference signal is coupled to the input of an adaptive quantizer (34) which provides at its output a bit compressed quantized differential PCM version of the difference signal. A multiplexer (37) receives the output of the quantizer and serves to periodically preempt the least significant bit of the bit compressed PCM signal and substitute a signaling bit therefor. The output of the multiplexer is coupled to the input of an adder (38) wherein it is added to the predicted signal. The result of this addition is coupled to the input of the predictor, which in response thereto serves to generate the next predicted signal for comparison with the next input signal sample. An adaptation control circuit (36) is responsive to the output of the multiplexer and serves to control the speed of adaptation of the adaptive quantizer.

Bit compression coding with embedded signaling

A data control circuit (18) for an input/output arrangement is arranged for controlling the transfer of a data word through a shift register (20 or 120) to or from a peripheral device (22 or 122). The circuit (18) provides for selection between internal clock generation at one of several rates or application of an external clock and for selection of the length and format of the data words to be transferred. Selection is accomplished by an interval counter (38), format data stored in a control register (37), two gating circuits (30 and 40) and a selection circuit (35).

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Stephen M Walters