Bell Communications Research, Inc.

Stephen M Walters

Masuma Ahmed

Daniel L Allen

Thierry Troudet

A system and method for operating a Broadband ISDN to support a viable virtual private network (VPN) service are attained by establishing a plurality of virtual path links connecting customer locations and broadband switching systems, by cross-connecting virtual channel links at the broadband switching systems to establish end-to-end virtual channel connections, and by policing both the input and output traffic only on the virtual path links. An egress policing processor is included at each output port on broadband switches to police the traffic on each virtual path link which contains one customer's multiplexed virtual channel connection traffic.

Broadband private virtual network service and system

A digital phase locked loop operable over a wide dynamic range has jitter performance that is exactly bounded within predetermined limits. The phase locked loop includes an accumulator-type digital voltage controlled oscillator (201) which generates from a high speed system clock, an output clock signal at frequency equal to p times the frequency of an input clock signal, and which output frequency is controlled by the value k of a digital input to the VCO. A frequency window comparator (208) compares the number of output clock pulses between input clock pulses to determine, based on the count, whether the frequency of the output is too high, too low or equal to the correct frequency. A phase window comparator (210) simultaneously determines from the phase of the output clock signal whether the phase is leading, lagging or within a prescribed window of acceptability. In response to these determinations, k-controller (217) increases k to increase the frequency of the VCO when the frequency window comparator indicates the frequency is low or the phase window comparator indicates the phase is lagging; alternatively, k is decreased when the frequency is high or the phase is leading. Adjustment continues until the output clock is at the proper frequency and phase of the output clock falls within the window of acceptability.

Digital phase locked loop with bounded jitter

In order to multiplex a plurality of various rate subchannels onto a fixed rate channel, a frame structure is defined consisting of j tuples of bits. Some of the tuples are i bits long and some are less than i, the sum of the bits less than i in these tuples being equal to k where k is greater than or equal to zero. The total number of bits per frame is thus equal to ij-k where i, j and k are mathematically determined as a function of the rates of the subchannels and the rate of the fixed channel. In one tuple of i bits in each frame, all bits are set ZERO. In each other tuple, the last bit is set ONE. Framing is detected by monitoring for a ONE followed by i ZEROes a pattern which cannot occur elsewhere in the frame regardless of the data. This frame arrangement can yield shorter frames than the frame structure disclosed in U.S. Pat. No. 4,617,658, thus decreasing reframe time.

Optimal frame arrangement for multiplexing a plurality of subchannels

A plurality of various rate digital subchannels are multiplexed onto a fixed rate channel by arranging the data bits from the subchannels into a framing structure consisting of j sets of i-tuples for ij bits per frame where the parameters i and j are mathematically determined as a junction of the rates of the subchannels and the rate of the fixed channel. Framing is maintained by setting each bit in the first i-tuple to ZERO and the last bit in each other i-tuple to ONE. A multiplexer-demultiplexer is described which is adaptive to the rates of the subchannels and the fixed channel in this frame structure and which can therefore be employed for any mix of subchannel and fixed channel rates. The multiplexer-demultiplexer includes a memory (204) for storing the bit assignment pattern for a frame structure configured for a particular mix of subchannel rates; plural subchannel interfaces (201-0--201-11) for storing bits directed to and from each channel and for clocking these bits onto and off the subchannels at their subchannel rates; and a kernel (203) which selects bits stored in the subchannel interfaces to form the multiplexed bit streams and distributes bits from the fixed channel to the subchannel interfaces in accordance with the stored bit assignment pattern. When a new bit assignment pattern is stored in the memory derived from a new combination of subchannel and fixed channel rates, the multiplexer-demultiplexer automatically adapts to the new frame structure and channel rates.

Adaptive rate multiplexer-demultiplexer

In order to multiplex a plurality of various rate subchannels onto a fixed rate channel, a frame structure is defined consisting of j sets of i-tuples for a total of ij bits per frame, the parameters i and j being mathematically determined as a function of the rate of the subchannels and the rate of the fixed channel. For j-l of the i-tuples, i-l bits are used for information and the last bit is set ONE. In one i-tuple all i bits are set ZERO. Framing is detected by monitoring for a ONE followed by i ZEROes, a pattern which cannot occur elsewhere in the frame regardless of the data. An integral number of information bits from each subchannel are distributed in the (i-l)(j-l) information bit positions. In the disclosed embodiment two 6662/3 bps channels and a 4800 bps channel are multiplexed onto an 8000 bps channel using a frame structure consisting of 24 quintets. In the 92 information bit positions, 72 bits are allocated for the 4800 bps channel and 10 bits each are allocated for the 6662/3 bps channels.

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Holmdel, NJ, United States of America

Stephen M Walters