Xilinx, Inc.

Other

Vlsi Technology, Inc.

Stephen M Trimberger

Austin H Lesea

Jennifer Wong

Richard A Carberry

Robert Anders Johnson

Khue Duong

Arifur Rahman

Raymond C Pang

F Erich Goetting

John E Mahoney

Charles R Erickson

Walter N Sze

Steven P Young

Bernard J New

Robert O Conn

Sundararajarao Mohan

Philip M Freidin

Jason J Moore

Michael J Hart

Kameswara K Rao

Adam P Donlin

David Bruce Parlour

John M Thendean

Brendan K Bridgford

Christopher H Kingsley

Weiguang Lu

Eric E Edwards

James D Wesselkamper

Wilson Kaming Yee

Danesh Tavana

Babak Ehteshami

Trevor J Bauer

Tim Tuan

Mohsen Hossein Mardi

Prasanna Sundararajan

James M Simkins

Venu M Kondapalli

Matthew H Klein

Eric R Keller

Derek R Curd

Bobby Yang

James Allely Rowson

Ting Lu

Gary R Lawman

David M Mahoney

Daniel Gitlin

Bart Reynolds

Hua Shen

Scott O Frake

Steven E McNeil

Chidamber R Kulkarni

James B Anderson

Brian Philofsky

Edward S Peterson

Jane W Sowards

Jonathan Scott Rose

William S Carter

Glenn O'Rourke

Edward S McGettigan

Reto Stamm

Xiao-Yu Li

Eric Thorne

Satyaki Das

Kam-Wing Li

Yuezhen Fan

Mon-Ren Chene

Alok Mehrotra

Subodh Gupta

Edel M Young

Mon R Chene

Pardner Wynn

Julia M Smuts

Christine M Weir

Todd J Topolewski

John C Hoffman

Benjamin J Stassart

Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.

Structure and method for a microelectronic device having high and/or low voltage supply

An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

Integration of a programmable device and a processing system in an integrated circuit package

Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes multiple lasers that input an electronic signal. Each laser encodes and outputs a respective optical data signal based on the electronic signal. Each laser has a different configuration of one or more first optical parameters. A first selection circuit selects the respective optical data signal from one of the lasers. Multiple optical components configure second optical parameters of an input optical data signal. A second selection circuit inputs the selected optical data signal from the first selection circuit and provides the selected optical data signal to one of the optical components. A third selection circuit selects the optical data signal output from the one optical component.

Optical communication circuits

A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.

Chip package assembly with power management integrated circuit and integrated circuit die

An example method of configuring a programmable integrated circuit (IC) in a computer system includes: selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system; selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit; providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric; generating configuration data for a circuit design having the first region, the second region, and the fence region; and loading the configuration data to the programmable IC.

Security for programmable devices in a data center

Disclosed approaches for protecting against attacks on a local network device include establishing an access period associated with one remote network device of a plurality of remote network devices. The router rejects messages from remote network devices of the plurality of remote network devices not having associated access periods. The router forwards to the local network device, a message received from the one remote network device during the access period. The router rejects, in response to expiration of the access period, subsequent messages from the one remote network device to the local network device.

Protection against attacks from remote network devices

Disclosed approaches for protecting against attacks on a network device, a second network device receives a first message from a first network device. In response to the first message, the second network device determines a first area from which the first network device issued the message. The second network device determines whether or not the first area intersects a second area having the second network device. In response to determining that the first area intersects the second area, the second network device acknowledges the first message to the first network device. In response to determining that the first area does not intersect the second area, the second network device rejects the first message.

Protecting local network devices against attacks from remote network devices

Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes a package substrate and f first interposer mounted on the package substrate. The apparatus also includes a logic circuit and an optical interface circuit connected to the logic circuit via the first interposer. One of the optical interface circuit or the logic circuit is mounted on the first interposer. The optical interface circuit includes a driver circuit configured to receive electronic data signals from the logic circuit. The optical interface circuit also includes an optical transmitter circuit coupled to the driver circuit and configured to output optical data signals encoding the electronic data signals.

The disclosure describes approaches for generating a physically unclonable function (PUF) value. Power is applied to a power control circuit, an SRAM, and a PUF control circuit. After initially powering-up the SRAM, the PUF control circuit signals the power control circuit to disable power to the SRAM. The power control circuit disables power to the SRAM, and then re-enables power to the SRAM after having power to the SRAM disabled for a waiting period. The PUF control circuit reads a PUF value from the SRAM by the PUF control circuit after the enabling of power.

SRAM physically unclonable function (PUF) circuit and method

A method and apparatus are provided that includes an electronic device, a chip package and a method for cooling a chip package in an electronic device. In one example, the chip package includes an interposer or package substrate having a first IC die and a second IC die mounted thereon. The second IC die has a maximum safe operating temperature that is greater than a maximum safe operating temperature of the first IC die. An indicia is disposed on the chip package. The indicia designates an installation orientation of the interposer or package substrate which positions the first IC die upstream of the second IC die relative to a direction of cooling fluid flow.

Lateral cooling for multi-chip packages

In an adaptation module relating generally to adaptive optical channel compensation, an analysis module is coupled to receive a first data signal and a second data signal and coupled to provide first information and second information. A comparison module is coupled to compare the first information and the second information to provide third information. An adjustment module is coupled to receive the third information to provide fourth information to compensate for distortion in the second data signal with reference to the first data signal. The second data signal is associated with a conversion of the first data signal to an optical signal for communication via an optical channel.

Adaptive optical channel compensation

Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations an optical communication device includes an optical data port configured to support an optical fiber in a fixed position. The optical communication device may further include a plurality of optical communication circuits, each oriented to communicate optical signals at a respective position of a cross section of the optical fiber connected to the optical data port and a control circuit, responsive to optical signals communicated on the optical fiber connected to the optical data port and configured to determine ones of the plurality of optical communication circuits that are misaligned with the optical fiber and disable the determined ones of the plurality of optical communication circuits.

A system includes an integrated circuit (IC) chip with connections to plurality of external pins. An integrated voltage regulator circuit is configured to provide an internal supply voltage to the IC chip. Isolation circuitry is configured to inhibit tampering of the internal supply voltage through the external pins. An analog to digital converter (ADC) circuit is configured to monitor parameters of the internal supply voltage. Security circuitry is configured to detect, using the monitored parameters, indications of tampering and to generate an error signal in response to detecting an indication of tampering.

Secure voltage regulator

Growing community of inventors

San Jose, CA, United States of America

Stephen M Trimberger