Intel Corporation

Stephen M Ramey

Ian A Young

Stefan Rusu

Uygar E Avci

Daniel Henry Morris

Rachael Jade Parker

David J Ayers

Kuan-Yueh Shen

Srikanth Balasubramanian

Zhiguo Wang

Suriya Suriya Ashok Kumar

Ketul B Sutaria

Sukirti Gupta

Various embodiments provide a health monitor circuit including an n-type sensor to determine a first health indicator associated with n-type transistors of a circuit block and a p-type sensor to determine a second health indicator associated with p-type transistors of the circuit block. The n-type sensor and p-type sensor may be on a same die as the circuit block. The health monitor circuit may further include a control circuit to adjust one or more operating parameters, such as operating voltage and/or operating frequency, for the circuit block based on the first and second health indicators. Other embodiments may be described and claimed.

On-die reliability monitor for integrated circuit

Techniques and mechanisms for changing a consistency with which a cell circuit ('cell') settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCl) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCl stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

Device, system, and method to change a consistency of behavior by a cell circuit

Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.

Semi-volatile embedded memory with between-fin floating-gate device and method

In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.

Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores

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North Plains, OR, United States of America

Stephen M Ramey