Lsi Logic Corporation

Hyundai Electronics America, Inc.

Symbios, Inc.

Ncr Corporation

At&t Global Information Solutions Company

Symbios Logic Inc.

Stephen M Johnson

John Matthew Adams

Timothy E Hoglund

David M Weber

Mark A Reber

Brian K Herbert

Jeffrey M Rogers

Jamey L Robbins

Nancy Holt

Michael R Hede

A method and apparatus for transmitting data in a node having a buffer. A first set of data is received in a buffer for transmission to a target node. The first set of data is sent to the target node. Responsive to an indication that the target node is unable to receive data, a second set of data is loaded into the buffer for transmission to another target node, while the first set of data is retained in the buffer.

Method and apparatus for transmitting Data

A method and apparatus in a source node for transmitting data to a target node. Responsive to a request to transmit data to the target node, a determination is made as to whether a selected period of time has passed without data transmitted from the source node being received by the target node. Responsive to detecting the selected period of time has passed without data transmitted from the source node being received by the target node, a determination is made as to whether space is available in the target node to receive the data. Responsive to a determination that space is unavailable in the target node, generating an indication that the target node is blocked is generated.

Method and apparatus for transmitting data to a node in a distributed data processing system

A method and apparatus for switching clocks comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal. The second circuit may be configured to generate a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal. The third circuit may be configured to select (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal.

Method and apparatus for switching clocks presented to synchronous SRAMs

The invention relates to data transfers between devices having asynchronous clocks. A FIFO having multiple levels holds the data while en route from a sender to a receiver. The invention monitors the FIFO. When all levels become full, the invention issues a FIFO_FULL signal. When all levels become empty, the invention issues a FIFO_EMPTY signal. In these signals, there are four events whose timing is important. (1) The ACTUATION of the FIFO_FULL is immediate; (2) the ACTUATION of the FIFO_EMPTY signal is immediate; (3) the DE-ACTUATION of the FIFO_FULL signal is synchronous with the clock of the computer reading the FIFO; (4) the DE-ACTUATION of the FIFO_EMPTY signal is synchronous with the clock of the computer writing to the FIFO. The invention allows throughput through the FIFO to proceed at a very high speed, even though the sender and receiver are asynchronous.

FIFO status indicator

A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received. A link control unit is provided in which loop management is provided when the host is connected to a loop. Management of the loop includes implementing mechanisms to initiate acquisition of the loop and initiate a release of the loop in response to conditions in which data is received and transmitted by the host and by other nodes on the loop.

Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion

A method and associated apparatus for using a primary FIFO and one or more secondary FIFOs in parallel to simplify flow control and routing in packet communication operations wherein at least one FIFO (buffer) is associated with each of a plurality of receiving nodes or components within a receiving node. The present invention applies received packets simultaneously to a primary FIFO and to all associated secondary FIFOs in the receiver of a packet communications link. After receipt of a packet, the packet is removed from any secondary FIFOs which correspond to receiver nodes or components to which the packet was not routed. For all receiving nodes or components to which the packet was routed, if the packet was stored in each associated secondary FIFO without overflow, then the packet is also purged from the primary FIFO. If any secondary FIFO overflowed by storage of the received packet, then the packet is purged from the overflowed FIFO and the packet remains stored in the primary FIFO for further processing. Flow control signals are generated and applied to the transmitting source as required in accordance with the status of the primary FIFO. The secondary FIFOs are not directly relevant to flow control logic. The receiving component corresponding to each secondary FIFO locates the next packet for processing by inspecting the associated secondary FIFO as well as the primary FIFO if the secondary FIFO overflowed. These methods and apparatus simplify flow control and routing control in packetized communication receivers.

Method and apparatus for using multiple FIFOs to improve flow control

A method and associated apparatus for automating the filtration and generation of information in a packetized communication system. A filtration table includes entries used in recognizing a valid packet received at a node in a communication system. A mask field in each entry is applied to appropriate fields in the packet (e.g. the ordered set as applied to Fibre Channel communication systems) to determine the validity of the packet with regard to the receiving node. Rules in a field of each entry further qualify the recognition of a received packet (e.g. ordered set) by testing the reception of the packet against other logical rules. Action fields in each record permit definition of actions to be invoked automatically (e.g. automatic adjustment of fill transmissions in Fibre Channel applications) in response to receipt and recognition of a particular packet. The set of packets recognized by the receiving node may be modified by adding, deleting, or modifying the entries in the filtration table. The programmable filtration thereby permits simple modifications to the protocol supported by the receiving node. Programmable generation capabilities of the present invention permit rapid integration of additional packets (e.g. ordered sets) transmitted in response to perceived packets in the receiving node. Programmable parameters in the receiving node permit automatic generation and transmission of packets in accordance with the parameter settings at the time of packet transmission.

Method and apparatus for programmable filtration and generation of

A method and apparatus for pseudo aligned transfers to memory for processors, peripherals and memories. Alignment logic, typically coupled to a peripheral, receives a plurality of data bytes from a processor. The alignment logic uses a control header transferred with the data bytes to determine whether the data bytes require re-alignment. To effect re-alignment, the alignment logic combines, rotates, and masks the data bytes as indicated by the control header.

Method and apparatus for pseudo-aligned transfers of data to memory

An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor information controlling the generation of its outline and its color pattern. When accessed, this cursor control data is accessed from the non-displayed segment of the memory during each horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Location of the cursor within the video display is determined by a group of position registers which are loaded by the CPU with cursor position data during the vertical blank time. The position registers in conjunction with a group of counters coordinate the insertion of the cursor data into a byte stream of display data as it makes its way to the CRT screen. This display data is stored in the frame buffer and is transferred to the pixel output buffer. The display data in the pixel output buffer is subsequently interpreted into colors and intensities, and displayed on the CRT screen using known techniques. The vertical and horizontal locations of the cursor are synchronously incremented on a pixel by pixel basis during the scan of a frame buffer line. At the appropriate location, cursor data is multiplexed and/or logically combined with the bit stream of frame buffer data to overlay the cursor characteristics upon the video display data. The cursor data buffer can thereby be relatively small yet overlay a relatively large cursor with minimal manipulation by the computer controlling the video display.

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Colorado Springs, CO, United States of America

Stephen M Johnson