Gsi Technology, Inc.

Giga Semiconductor, Inc.

Stephen Lee

Lee-Lean Shu

Chenming W Tung

The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the DRAM array to be refreshed. Address control and switching circuitry may be coupled to the refresh control circuitry. The address control and switching circuitry selectively transmits read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations.

System and method for refreshing a DRAM device

A voltage down converter for providing a supply voltage and current to a device, such as a semiconductor device. The voltage down converter includes a first circuit that supplies steady state or &ldquo;DC&rdquo; current to the device, and a second circuit that supplies the fluctuating or &ldquo;AC&rdquo; current to the device. The first circuit includes a first comparator that drives a first transistor P to supply most of the steady state current. The second circuit includes a second comparator , which is larger than the first comparator , and which drives a second transistor P , which is smaller than the first transistor P , to supply the fluctuating current to the device. The converter further includes a feedback circuit for controlling the supply voltage.

Voltage down converter

The present invention provides data coherent logic for an SRAM device. The present invention utilizes a data strobe signal and an output strobe signal to control data written into and read out of the. SRAM device from an input/output pad. Data coherent logic is designed to resolve timing conflicts between the data and output strobe signals. The logic selectively delays the output strobe signal when a match occurs for data requested in a read operation immediately following a write operation. The delay allows sufficient time for the data to be registered and selected before being outputted from the device.

Growing community of inventors

Campbell, CA, United States of America

Stephen Lee