International Business Machines Corporation

Stephen Larry Runyon

Jason D Hibbeler

Robert F Walker

Kevin W McCullen

Rani Narayan

Robert K Montoye

Fook-Luen Heng

Fariborz Assaderaghi

Nancy Anne Greco

Scott R Stiffler

Matthew Thomas Guzowski

Harold Wayne Chase

Myhong Nguyenphu

Kenneth L DeVries

Veit Gernhoefer

Daniel Cocanougher

Joan Preston

Joseph Roland Verock

Lars W Liebmann

Shreesh Narasimha

Peter Juergen Klim

Christopher McCall Durham

K Paul Muller

James A Culp

Leon Jacob Sigal

Michael S Gray

Rajeev Malik

Xin Yuan

Patrick M Williams

Eric Bernard Schorn

Robert T Sayah

Steven Eugene Washburn

Matthew J Amatangelo

Pieter J Woeltgens

Xiaoyun K Wu

Roy Smythe Bass, Jr

Bruce C Wheeler

The invention includes a solution for selectively scaling an integrated circuit (IC) design by: layer, region or cell, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield.

Integrated circuit selective scaling

A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.

Layout optimization using parameterized cells

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Methods for charge dissipation in integrated circuits

An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

OPC trimming for performance

Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.

Independent migration of hierarchical designs with methods of finding and fixing opens during migration

Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.

Ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits

Method and structure for charge dissipation in integrated circuits

A system and method for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment of the present invention, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.

System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits

Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

A capacitor structure ( ) is implemented in an integrated circuit chip ( ) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body ( ) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions ( ) on both lateral sides of this device body ( ). These lateral regions ( ) are formed from a second semiconductor material. A dielectric layer ( ) is formed over both lateral regions ( ) and the device body ( ), while an anode layer ( ) is formed over the dielectric layer in an area defined by the device body. Each lateral region ( ) is coupled to ground at a first end ( ) of the elongated device body ( ). The anode ( ) is coupled to the chip supply voltage at a second end ( ) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Method for producing an integrated circuit capacitor

An EQUATE property is introduced into the layout cell data for a layout design to identify the schematic to which the layout design corresponds. Rather than exploding the layout cell up to the next level for flat checking because the equivalent schematic is not known, the layout cell instances may then be checked hierarchically, with one instance checked internally for compliance with design rules and the like while the remaining instances are merely checked for proper connection to neighboring cells. New layout cell designs may therefore be created as the need arises during layout without requiring schematic checking tools to be rerun.

Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips

Layout cells having the same name as a corresponding schematic are checked hierarchically, with a single instance of a particular layout cell being checked internally for compliance with design rules and the like while remaining instances are merely checked for proper connection to neighboring cells. Layout cells which are not named the same as any schematic are automatically exploded for flat checking at the transistor level. Thus hierarchical checking is preserved for those layout cell instances named for the corresponding schematic, which should be the large majority of cell instances in any given integrated circuit, while cell instances meeting special layout requirements, which should be a small number of cases, are supported for any given schematic.

Invention to allow hierarchical logical-to-physical checking on chips

A method and system are disclosed for improving a yield of circuits produced from a semiconductor wafer. A plurality of design rules are established for designing a layout of the circuit within the wafer. A yield-limiting set of the plurality of design rules are selected. Adherence to each of the set of rules throughout all of the layout reduces the yield. For each one of the set of rules, a recommended value is determined. A percentage of occasions each one of the set should be exceeded within the layout is also determined. The layout is then designed so that each one of the set of the plurality of design rules meets or exceeds the recommended value more often than the percentage.

Method and system for improving yield of semiconductor integrated circuits

The method includes defining at least one sizing parameter for a capacitor arrangement ( ). Once the parameter or parameters are defined, the method includes applying at least one sizing parameter to select a particular capacitor arrangement ( ) for a free area on the integrated circuit chip ( ). The selected capacitor arrangement comprises the largest arrangement which is accommodated within the free area, subject to the sizing parameter or parameters employed. Sizing parameters may include a height dimension range between a maximum and minimum height dimension for the capacitor arrangement, and permissible width dimensions for the capacitor arrangement. Steps in the layout method may be performed on a computer system ( ) under the control of operational program code.

Method, apparatus, and program product for laying out capacitors in an integrated circuit

A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.

Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets

Growing community of inventors

Pflugerville, TX, United States of America

Stephen Larry Runyon