Morphics Technology, Inc.

Infineon Technologies Ag

Xilinx, Inc.

Stephen L Wasson

John D Ralston

David K Varn

Gary R Lawman

Joseph D Linoff

A digital logic circuit comprises a programmable logic device and a programmable security circuit. The programmable security circuit stores a set of authorized configuration security keys. The programmable security circuit compares the authorized configuration security keys with an incoming configuration request, and selectively enables a new configuration for the programmable logic device in response to the configuration request. In another exemplary embodiment, a programmable security circuit also stores a set of authorized operation security keys. The programmable security circuit compares the authorized operation security keys with an incoming operation request from the programmable logic device, and selectively enables an operation within the programmable logic device in response to the operation request.

Apparatus and method for a programmable security processor

A signal control circuit includes a set of signal lines that form a data bus. A set of three-state driver columns is connected to the data bus; each three-state driver column is connected to each signal line of the set of signal lines. A programmable synchronous three-state control circuit is connected to the set of three-state driver columns. The programmable synchronous three-state control circuit responds to a control signal and select signals to produce a three-state output enable signal which is applied to a selected three-state driver column of the set of three-state driver columns so as to control data signals on the data bus.

Apparatus and method for controlling a three-state bus

A method of designing a circuit includes the step of establishing a matrix of circuit modules including sub-sets of circuit modules. A slice of circuit modules aligned along a first axis is selected from the matrix of circuit modules. The slice of circuit modules is replicated along a second axis to construct a logic structure with uniform height and width.

Apparatus and method for designing a circuit using minimum slice construction and replication

A programmable data arithmetic array includes a set of data buses and a matrix of data arithmetic units including fixed function units and programmable function units connected to the set of data buses. Bidirectional interconnect is positioned between the set of data buses and the matrix of data arithmetic units.

Apparatus and method for programmable datapath arithmetic arrays

A heterogeneous programmable gate array has an unstructured logic sub-array and a structured logic sub-array. An unstructured input/output interconnect structure delivers unstructured-to-unstructured input/output signals to the unstructured logic sub-array, while a bussed input/output interconnect structure delivers structured-to-structured input/output signals to the structured logic sub-array. A control signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver unstructured source signals therebetween. A bussed signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver structured source signals therebetween.

Heterogeneous programmable gate array

An interleaved signal carry structure includes a first signal line and a second signal line forming a first bus. A third signal line and a fourth signal line form a second bus. A first set of carry function generators are positioned between the first signal line and the third signal line. Carry-in signal lines are attached to the first set of carry function generators. A second set of carry function generators are positioned between the second signal line and the fourth signal line. Intermediate carry signal lines are positioned between the first set of carry function generators and the second set of carry function generators. Carry out signal lines are attached to the second set of carry function generators. A first vertical carry chain comprises a first carry function generator from the first set of carry function generators and a first carry function generator from the second set of carry function generators. A second vertical carry chain comprises a second carry function generator from the first set of carry function generators and a second carry function generator from the second set of carry function generators.

Apparatus and method for interleaving a signal carry chain in an integrated circuit

A programmable logic device includes an array of logic modules. A standard interconnection grid, with vertical routing lines, horizontal routing lines, and local routing lines, links the array of logic modules. An omniversal bus is positioned over the array of logic modules. The array of logic modules includes selective links to the omniversal bus, such that the omniversal bus dynamically establishes autonomous sub-arrays of logic modules of variable size attached to the omniversal bus.

Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array

A table-based computer user interface and a method of providing design parameters are provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for application-specific circuits and other complicated circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters and memory map data are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. In one embodiment, the user interface can also be used to display read data from a previously programmed programmable IC.

Growing community of inventors

Boulder Creek, CA, United States of America

Stephen L Wasson