Motorola Corporation

Other

Stephen L Smith

James Douglas Dworkin

John Michael Buss

Shay-Ping T Wang

Scott Edward Lloyd

Shao Wei Pan

ShaoWei Wei Pan

Kuppuswamy Raghunathan

Dean W Mueller

Philip B Giangarra

Jeffrey R Jorvig

A programmable versatile digital signal processing system architecture (FIG.,) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG.,) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (FIGS.,and,).

Versatile digital signal processing system

A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (1300, 1400, 1500, 1600).

Hybrid instruction set for versatile digital signal processing system

An enclosure for small animals, such as rodents, is described wherein the enclosure is constructed of various component parts. The component parts of the enclosure can be easily replaced when either damaged or destroyed, thus eliminating the need to replace the entire enclosure. The enclosure can also be rapidly assembled and disassembled without the need for any tools or mechanical ability. The enclosure's component parts may be constructed of any suitable thermoplastic material, wherein the thermoplastic material can be either opaque, translucent, or transparent.

Enclosure for small animals

A computational array includes a self timed computational element that performs self timed calculations internally independent of a global clock. The self timed computational element includes a computational unit (100) which produces a complete signal upon the completion of calculation of a result value. The self timed computational element also includes a self timed control unit (200) which determines whether a new result value is to be calculated by the computational unit (100) based on an iteration signal which indicates a number of times the new result value is to be calculated, and based on the complete signal received from the computational unit (100) indicating that each previous calculation has been completed. Upon determining that a new result value is to be calculated, the self timed control unit (200) provides a self timed clock signal to the computational unit (100) and the computational unit (100) calculates the new result value accordingly.

Computational array with self timed computational element and method of

A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

Exponentiation circuit utilizing shift means and method of using same

A computational array circuit (100) performs parallel multiplications with an adder array (140). The computational array circuit converts a floating point input value to a logarithmic input value. The logarithmic input value is then added to a logarithm of a multiplier value by an adder circuit (145) in each of a number of array elements (150) of the adder array (140). The computational array circuit (100) converts the resulting logarithmic output value from each of the array elements (150) to an antilogarithmic output value. The antilogarithmic output value from each of the array elements is thus the mathematical equivalent of the floating point input value multiplied by the multiplier value. The computational array circuit (100) thus obtains the advantage of floating point precision and range while requiring far less physical area than floating point multipliers would require to perform the same functions.

Computational array circuit for providing parallel multiplication

A converter which may be used for implementing either logarithmic or inverse-logarithmic functions includes a memory, a multiplier, and an adder. The memory stores a plurality of pre-computed values which are used in an interpolation to estimate a logarithmic or inverse-logarithmic function over a domain of input signals.

Logarithm/inverse-logarithm converter utilizing linear interpolation and

A support for boat oars to hold the oars in a fixed stationary and at rest position without the use of the rower's hands. The support is of particular use in a single sculling boat and consists of securing oar straps fastened to a bar. An overall riser rod assembly is formed by placing upper and lower riser rods on a connecting rod. The overall riser rod assembly is pivotally connected at one end to a plate attached to the bar and, at the other end, to a plate attached to a mounting bracket. The mounting bracket is fastened to the structure of the boat. The overall riser rod assembly can be adjusted in length to conform to various boats and rowers. The support is easily lowered to an out of the way location when not in use.

Support for boat oars

A combinational static CMOS logic circuit for providing a plurality of basic two-input logic functions with reduced complexity and integrated circuit area. The combinational static CMOS logic circuit provides either a NAND or an XOR output at a first output terminal and a NOR output at a second output terminal. A configuration input terminal is utilized for selecting between the NAND or the XOR output being provided at the first output terminal. In an alternate configuration, the combinational static CMOS logic circuit provides either a NOR or an XNOR output at a first output terminal and a NAND output at a second output terminal.

Combinational static CMOS logic circuit

A linkage is provided for interconnecting two horizontally spaced bodies so that relative vertical movement of the two bodies occurs in a linear path. The linkage comprises a link member having universal pivotal connection to one of the bodies, for example the wheel hub of an automobile. The other end of the link is deformed into a vertical planar configuration and defines a vertically curved slot and a horizontal slot horizontally spaced from the vertically curved slot. Two horizontal pins are rigidly affixed to the other body, for example the chassis or frame of the automobile, and respectively traverse the vertically curved and horizontal slots with the result that the wheel hub can only move in a generally vertical direction relative to the frame along a linear path.

Wheel suspension linkage

A high voltage CMOS decoder and level translator for use in conjunction with EPROMS and EEPROMS utilizes additional series coupled field effect transistors maintained in an on condition so a to prevent the voltage across the pull-up and pull-down field effect transistors from exceeding their break down voltages. For example, in addition to a pull-up P-channel field effect transistor and a pull-down N-channel field effect transistor in the output inverter circuit, additional P-channel and N-channel field effect transistors are coupled in series between the pull-up and pull-down transistors to maintain the voltage across the pull-up and pull-down transistors from exceeding there breakdown voltages.

High voltage decoder

An E.sup.2 PROM redundant memory element is provided whereby faulty or improperly coded ROM or E.sup.2 PROM elements may be replaced by the user in-package. An address programming element including an E.sup.2 PROM floating gate device having a programmed mode, an unprogrammed mode, and an inhibit mode, may be programmed and erased in-package. Addresses received by the redundant memory element in addition to other inputs determine the mode of the floating gate device.

In-package E.sup.2 PROM redundancy

An insulated-gate field-effect-transistor (IGFET) quasi-static decoder for programming an electronically-programmable read-only memory (EPROM) applies to the floating gate of selected memory devices a programming voltage. Prior to selection, each row and column conductor of the memory is latched at a first voltage. Precharge circuitry responsive to a single precharge pulse establishes an enabling voltage for unlatching a selected row and column. The selected row and column is then coupled via a switch to a source of programming voltage.

Apparatus for programming a dynamic EPROM

An NMOS voltage regulator circuit generates a reference voltage for comparison with, for example, TTL logic levels. A resistive voltage divider coupled to a 5 volt source produces a voltage of, for example, 1.5 volts which is applied to the non-inverting input of a differential amplifier. The reference voltage appears at the inverting input of the differential amplifier. Field effect transistor means are provided to raise or lower the voltage at the inverting input depending on whether a negative or positive excursion has taken place.

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Chandler, AZ, United States of America

Stephen L Smith