Synaptics Corporation

Ati Technologies Ulc

Ati International Srl

Ati Technologies Inc.

Advanced Micro Devices Corporation

Adeia Semiconductor Bonding Technologies Inc.

Broadcom Corporation

Stellar Semiconductor, Inc.

Qualcomm Incorporated

Invensas LLC

Synaptics Incorported

Stephen L Morein

Joseph Kurth Reynolds

Andrew Evan Gruber

Laurent Lefebvre

Jeffrey Lukanc

Petr Shepelev

Christopher A Ludden

Lin Chen

Ming-Ju Edward Lee

Joseph D Macri

Andi Skende

Greg P Semeraro

Claude R Gauthier

Mark Stefan Grossman

Michael C Lewis

Prashant Shamarao

Javier A DeLaCruz

Jeffrey Alan Small

Larry D Seiler

Mark Fowler

Damien Berget

Belgacem Haba

Rajesh Katkar

Vineet Goel

Kasra Khazeni

David A Sobel

Thomas A Mackin

Philip J Rogers

Imre Knausz

Robert Scott Hartog

Robert Bloemer

Peijun Shan

Marshall Bell

Shriram Kulkarni

Shahin Solki

Michael Doggett

Ilyas Mohammed

Guozhong Shen

Patrick Smith

Kirk Hargreaves

Warren Fritz Kruger

Marshall J Bell, Jr

Mohamed Ashraf Sheik-Nainar

Anna Ostberg

Andrew C Hsu

Jason Goodelle

Xu Chang

Eric Faggin

Daniel L Odell

Richard Bagley

Kevin M Olson

Zhibing Liu

Brian Etscheid

Jay C Wilkinson

Tai-Chien Liu

Daniel Jamison

Jocelyn Houle

Tom E Frisinger

Mark A Natale

Richard G Fadden

Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

Diffused bitline replacement in memory

Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.

Over and under interconnects

A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Multi-thread graphics processing system

This disclosure generally provides an input device that includes multiple sensor and display electrodes and a processing system. The processing system includes a plurality of local receivers coupled to respective ones of the sensor electrodes, where the local receivers are configured to acquire first resulting signals from the sensor electrodes. The processing system also includes a central receiver coupled to the sensor electrodes and configured to acquire second resulting signals from each of the sensor electrodes.

Central receiver for performing capacitive sensing

Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

Diffused bitline replacement in stacked wafer memory

A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Graphics processing architecture employing a unified shader

A system and method for thinning an integrated circuit (IC) wafer. The system includes a support structure to hold the IC wafer and a mechanism to operate on the IC wafer. The support structure includes one or more inductive coils configured to transmit a power signal to the IC wafer and receive a feedback signal from the IC wafer. The system further includes a process controller to control the operation based at least in part on the feedback signal received from the IC wafer.

Process monitor for wafer thinning

Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.

Stacked architecture for three-dimensional NAND

A method and apparatus for overdriving pixel elements to a desired voltage. A display device comprises a pixel array and overdrive circuitry to determine a current pixel value for a first pixel element of the pixel array and a target pixel value for the first pixel element. The overdrive circuitry is further configured to determine a first voltage to be applied to the first pixel element to cause the first pixel element to transition from the current pixel value to the target pixel value by a first instance of time. The first voltage is determined based at least in part on a position of the first pixel element in the pixel array. The display device further comprises a data driver to apply the first voltage to the first pixel element before the first instance of time and a backlight to illuminate the pixel array at the first instance of time.

Dynamic overdrive for liquid crystal displays

A method and apparatus for updating pixel elements of a display device. The display device comprises a pixel array including a plurality of pixel elements and one or more light sources to illuminate the pixel array at a first instance of time. A data driver is configured to receive a frame of display data corresponding to an image to be displayed on the pixel array at a first instance of time. The data driver scans each row of the pixel array, during a pixel adjustment period prior to the first instance of time, to drive a plurality of first voltages onto the plurality of pixel elements, respectively, based on the received frame. The data driver further rescans a subset of rows of the pixel array, during the pixel adjustment period, to drive second voltages onto respective pixel elements in the subset of rows based on the received frame.

Display rescan

A method of transporting foveal image data is disclosed. A host device receives image data from an image source and renders a full field-of-view (FFOV) image using the image data. The host device further identifies a foveal region of the FFOV image and renders a foveal image corresponding to the foveal region using the image data. More specifically, the foveal image may have a higher resolution than the foveal region of the FFOV image. The host device may then transmit each of the foveal image and the FFOV image, in its entirety, to a display device. For example, the host device may concatenate the foveal image with the FFOV image to produce a frame buffer image, and then transmit the frame buffer image to the display device.

Display interface with foveal compression

A microelectronic package may include a substrate having first and second surfaces each extending in first and second directions, a NAND wafer having a memory storage array, a bitline driver chiplet configured to function as a bitline driver, and a wordline driver chiplet configured to function as a wordline driver. The NAND wafer may be coupled to the first surface of the substrate, and the bitline and wordline driver chiplets may each be mounted to a front surface of the NAND wafer. The NAND wafer may have element contacts electrically connected with conductive structure of the substrate. The bitline and wordline driver chiplets may be elongated along the first and second directions, respectively. Front surfaces of the bitline driver chiplet and the wordline driver chiplet may be arranged in a single common plane and may be entirely contained within an outer periphery of the front surface of the NAND wafer.

Abstracted NAND logic in stacks

Growing community of inventors

San Jose, CA, United States of America

Stephen L Morein