Synaptics Corporation

Ati Technologies Ulc

Ati International Srl

Ati Technologies Inc.

Advanced Micro Devices Corporation

Intel Corporation

Adeia Semiconductor Bonding Technologies Inc.

Broadcom Corporation

Stellar Semiconductor, Inc.

Qualcomm Incorporated

Adeia Semiconductor Technologies LLC

Invensas LLC

Synaptics Incorported

Stephen L Morein

Joseph Kurth Reynolds

Andrew Evan Gruber

Laurent Lefebvre

Jeffrey Lukanc

Petr Shepelev

Christopher A Ludden

Lin Chen

Ming-Ju Edward Lee

Joseph D Macri

Andi Skende

Greg P Semeraro

Adel A Elsherbini

Feras Eid

Claude R Gauthier

Mark Stefan Grossman

Michael C Lewis

Prashant Shamarao

Aleksandar Aleksov

Javier A DeLaCruz

Georg Seidemann

Bernd Waidhas

Jeffrey Alan Small

Larry D Seiler

Mark Fowler

Damien Berget

Lizabeth Keser

Belgacem Haba

Rajesh Katkar

Georgios C Dogiamis

Henning Braunisch

Vineet Goel

William J Lambert

Yoshihiro Tomita

Kasra Khazeni

David A Sobel

Thomas A Mackin

Philip J Rogers

Imre Knausz

Robert Scott Hartog

Beomseok Choi

Carlton E Hanna

Robert Bloemer

Shahin Solki

Shriram Kulkarni

Peijun Shan

Marshall Bell

Wenhao Li

Michael Doggett

Johanna M Swan

Ilyas Mohammed

Guozhong Shen

Patrick Smith

Kirk Hargreaves

Kaladhar Radhakrishnan

Krishna Bharath

Warren Fritz Kruger

Marshall J Bell, Jr

Mohamed Ashraf Sheik-Nainar

Anna Ostberg

Jason Goodelle

Andrew C Hsu

Xu Chang

Eric Faggin

Ahmed Abou-Alfotouh

Kevin M Olson

Richard Bagley

Daniel L Odell

Jay C Wilkinson

Edward Lee

Zhibing Liu

Brian Etscheid

Daniel Jamison

Richard G Fadden

Mark A Natale

Tom E Frisinger

Tai-Chien Liu

Jocelyn Houle

Carlton Hanna

Lee E Ming-Ju

Chen Lin

Robert W Bloemer

Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

High throughput additive manufacturing for integrated circuit components containing traces with feature size and grain boundaries

Technologies for high throughput additive manufacturing for integrated circuit components

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.

Microelectronic assemblies having topside power delivery structures

In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.

A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material.

Modular microchannel thermal solutions for integrated circuit devices

Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

Embedded metal lines

An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

High-throughput additively manufactured power delivery vias and traces

Diffused bitline replacement in memory

Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.

Over and under interconnects

A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Multi-thread graphics processing system

This disclosure generally provides an input device that includes multiple sensor and display electrodes and a processing system. The processing system includes a plurality of local receivers coupled to respective ones of the sensor electrodes, where the local receivers are configured to acquire first resulting signals from the sensor electrodes. The processing system also includes a central receiver coupled to the sensor electrodes and configured to acquire second resulting signals from each of the sensor electrodes.

Central receiver for performing capacitive sensing

Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

Diffused bitline replacement in stacked wafer memory

A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Graphics processing architecture employing a unified shader

Growing community of inventors

San Jose, CA, United States of America

Stephen L Morein