Eastman-Kodak Company

Stephen L Kosman

Eric Gordon Stevens

Constantine N Anagnostopoulos

David N Nichols

Paul L Roselle

David L Losee

Win-Chyi Chang

James P Lavine

William G America

Yawcheng Lo

Christopher R Hoople

Loretta R Fendrock

Patricia A Mahns

An image sensor includes a substrate having photosensitive areas; an insulator spanning at least a portion of the substrate; and a first and second layer of a multi-layer metallization structure, wherein the first layer forms light shield regions over selected portions of the photosensitive area as well forming circuit interconnections and barrier regions to prevent spiking into the substrate or gates at contacts in the non-imaging area; and the second layer spanning the interconnections and barrier regions of the first layer only over the non-imaging areas and the second layer overlays edges of the first layer.

Method of thin lightshield process for solid-state image sensors

An image sensor includes a substrate having photosensitive areas; an insulator spanning the substrate; and a first and second layer of a multi-layer metallization structure, wherein the first layer forms light shield regions over selected portions of the photosensitive area as well forming circuit interconnections and barrier regions to prevent spiking into the substrate or gates at contacts in the non-imaging area; and the second layer spanning the interconnections and barrier regions of the first layer only over the non-imaging areas and the second layer overlays edges of the first layer.

Thin lightshield process for solid-state image sensors

An image sensor includes a semiconductor substrate; a photosensor having, a first photosensing region including a first stack of one or more layers of transparent materials covering the substrate, the first photosensing region having a spectral response having minima and maxima as a function of wavelength of light; a second photosensing region including a second stack of one or more layers of transparent materials covering the substrate, the second photosensing region having a spectral response having maxima and minima; and a third photosensing region including a third stack of one or more layers of transparent materials covering the substrate, the third photosensing region having a spectral response having maxima and minima; and wherein at least one maximum or minimum of the spectral response of the separate regions is matched with a minimum or maximum such that the average spectral response of the photosensor has less variation with wavelength of light than the individual spectral responses of each of the separate photosensing regions.

Image sensor with improved optical response uniformity

An image sensor, includes a semiconductor substrate; a photosensor having, a first photosensing region including a first stack of one or more layers of transparent materials overlying the substrate, the first photosensing region having a spectral response having peaks and valleys, and a second photosensing region including a second stack of one or more layers of transparent materials overlying the substrate, the second photosensing region having a spectral response having peaks and valleys; and wherein at least one peak or valley of the spectral response of the first region is matched to at least one valley or peak respectively of the spectral response of the second region such that the average spectral response of the photosensor is smoother than the individual spectral response of either the first or second photosensing regions.

Image sensor having improved spectral response uniformity

A method and apparatus of making high energy implanted photodiode that is self aligned with the transfer gate, the high energy implant is defined by providing a substrate, or well, of a first conductivity type, defining a charge coupled device within the substrate, or well, such that gate electrode layers are allowed to exist over areas to contain photodiodes during construction of the charge coupled device, patterning a masking layer to block high energy implants such that openings in the masking layer are formed over the areas of the photodiodes, anisotropically etching down through the gate electrode over the photodiodes to the gate dielectric material, implanting photodiodes with high-energy ions of a second conductivity type opposite the first conductivity type and creating a pinned photodiode by employing a shallow implant of the first conductivity type. The apparatus made by this method yields a photodiode employing high energy ions to form the P/N junction that is self aligned with the transfer gate.

Method of making self-aligned, high-enegry implanted photodiode for solid-state image sensors

By incorporating an ITO electrode which is more transparent than polysilicon, and designing the pixel such that it has asymmetric gates with as much as possible of its light sensitive region covered by an ITO electrode, light sensitivity is increased. To solve the problem of impurity diffusion from the ITO electrode into the silicon below, the conventional Silicon Dioxide gate dielectric was replaced with an Oxide/Nitride/Oxide stack. Employing at least some polysilicon electrodes with ITO electrodes is desirable to allow entrance passages through which hydrogen passivation can be accomplished. The pixel architecture can be designed to increase sensitivity further by other design choices. The first of these choices is to incorporate a lenslet on each pixel such that as much as possible of the light falling on the pixel is made to pass through the portion of the pixel covered with ITO. The pixel light sensitivity improves not only because the light passes through the more transparent ITO electrode, but also because some of the light that would have fallen on the LOD region and would be lost, is now collected. The second method is for color CCD sensors with color filter patterns, such as the 'BAYER' color filter pattern to name just one, to have the overlap of the color filters, which does not allow light transmission, to occur over the less sensitive area of the pixel, which is the area covered with the polysilicon electrode. For proper operation a slight modification of the vertical clock timing is needed.

Method of fabricating a image sensor having ITO electrodes with

Image sensor having ITO electrodes with an ONO layer

By designing pixels with highly transparent ITO electrodes and asymmetric gates such that as much light as possible falls upon a region covered by an ITO electrode, light sensitivity is increased. Impurity diffusion from the ITO electrode into the silicon below is prevented by employing an Oxide/Nitride/Oxide stack as a dielectric. Employing at least some polysilicon electrodes with ITO electrodes is desirable to allow entrance passages through which hydrogen passivation can be accomplished. The pixel architecture can be designed to increase sensitivity further by other design choices. The first of these choices is to incorporate a lenslet on each pixel such that as much as possible of the light falling on the pixel is made to pass through the portion of the pixel covered with ITO. The second method is for color CCD sensors with color filter patterns, such as the 'BAYER' color filter pattern to name just one, to have the overlap of the color filters, which does not allow light transmission, to occur over the less sensitive area of the pixel, which is the area covered with the polysilicon electrode. For proper operation a slight modification of the vertical clock timing is needed.

Image sensor having ITO electrodes with overlapping color filters for

A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.

Self aligned antiblooming structure for solid state image sensors

An insitu image reversal process which uses a sacrificial coating of indium tin oxide and simultaneously deposits amorphous carbon in openings patterned in the ITO while removing the deposited ITO to expose the underlying coating, thereby completing image reversal.

Low temperature insitu image reversal process for microelectric

The present invention is directed to a method of making a true two-phase CCD using a single layer (level) of the conductive material for the gate electrodes to provide a planar structure. The method includes using L-shaped masking layers having a submicron length of a bottom portion between two masking layers of silicon dioxide on and spaced along a surface of a conductive layer. The conductive layer is over and insulated from a surface of a body of a semiconductor material having a channel region therein. The L-shaped masking layers are removed to expose a spaced narrow portions of the conductive layer. The conductive layer is then etched completely therethrough at each exposed portion to divide the conductive layer into gate electrodes which are spaced apart by submicron width gaps.

Method of making two-phase buried channel planar gate CCD

A method of making a two-phase charge coupled device (CCD) includes forming a layer of a conductive material over and insulated from the surface of a body of a semiconductor material of one conductivity type having a channel region of the opposite conductivity type in the body and extending to the surface. Sections of a first masking layer are formed on the conductive material layer spaced along the channel region. A conductivity modifying dopant is implanted into the channel region through the spaces between the sections of the first masking layer. A layer of a second masking layer is formed over the sections of the first masking layer and on the surface of the conductive material layer in the spaces between the sections of the first masking layer. A layer of indium-tin oxide (ITO) is formed over the portions of the second masking layer which extend across the ends of the sections of the first masking layer, and a layer of carbon is formed on the second masking layer between the ITO layers. The ITO layers along the ends of the sections of the first masking layer are then removed, and exposed portions of the second masking layer are removed. The portions of the conductive material layer under the removed portions of the second masking layer are then removed so as to leave the conductive material layer divided into individual very closely spaced apart (submicron spacing) gate electrodes.

Method of making two-phase charge coupled device

A method of forming a planar ITO gate electrode structure with sub-micron spacing includes forming L-shaped nitride spacer portions.

Growing community of inventors

Rochester, NY, United States of America

Stephen L Kosman