Hewlett-packard Development Company, L.p.

Stephen L Bass

Glenn T Colon-Bonet

Rohit Bhatia

Thomas Justin Sullivan

Ravi G Koshy

Methods and apparatus for stalling a pipeline, which methods and apparatus allow data in speed critical pipeline stages to propagate through additional stages of the pipeline. The data is then 'caught' and stored in a deferred stall register as it is output from a downstream pipeline stage X. Finally, the data is output from the deferred stall register in a way that it masks the regular output of the pipeline stage X. In this manner, there is no need to store stalled data in a speed critical pipeline stage. Rather, the data can slip ahead, be saved, and be output at an appropriate time such that it appears that the data was stalled in the pipeline stage in which it existed at the time a stall was initiated.

Method and apparatus for preserving pipeline data during a pipeline stall and for recovering from the pipeline stall

The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus includes a first array of odd/even summation circuitry, a second array of odd/even summation circuitry, and a linear array of adders. The apparatus is configured to add a row of partial product bits produced by a multiplier in multiplying a first operand with a second operand. The first array of odd/even summation circuitry produces a first summation of a portion of the partial product bits. The second array of odd/even circuitry produces a second summation of the other partial product bits. The linear array of adders then adds the first summation and the second summation to produce a carry save representation of a product bit (i.e., a bit of the product produced by multiplying the first operand by the second operand).

Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry

An apparatus and method provide for performing either an overflow or underflow comparison while minimizing overflow/underflow comparison circuitry. In particular, the apparatus and are implemented with overflow/underflow possible check circuitry that determines if a mathematical operation between a first exponent signal and a second exponent signal creates a potential overflow condition. The overflow/underflow possible check circuitry generates a signal indicating whether an overflow or underflow condition is a possibility. Exponent compare circuitry computes an actual overflow or underflow condition. The exponent compare circuitry computes an actual overflow condition if the signal, from the overflow/underflow possible check circuitry, indicates that overflow is possible, and computes an actual underflow condition if the signal, from the overflow/underflow possible check circuitry, does not indicate overflow is possible.

Apparatus and method for sharing overflow/underflow compare hardware in a floating-point multiply-accumulate (FMAC) or floating-point adder (FADD) unit

A selection based rounding system and method eliminate the need for post increment based rounding in a floating point (FP) fused multiply adder that can be utilized in a processor or other digital circuit to significantly increase speed. Generally, an unincremented result and an incremented result are produced in parallel and then either one is selected as a rounded result based upon specified rounding criteria, thereby eliminating the time consuming need for an incrementor to perform rounding at or near the end of the FP fused multiply adder.

Selection based rounding system and method for floating point operations

A floating-point multiply accumulate method acquiring a final mantissa result comprises comparing exponents of (A*B) and C. Transferring part of the C mantissa to a CHI register. Shifting any part of the C mantissa which overlaps the range of the (A*B) mantissa to align the bits of the (A*B) and C mantissas. Adding the shifted part of the C mantissa to the (A*B) mantissa. Shifting least significant bits corresponding to a number of bits transferred to the CHI register out of the Temp. Result. Mask merging bits of the C mantissa which were transferred to the CHI register with most significant bit positions of the shifted Temp. Result. Rounding this mantissa result to the first precision and acquiring L from an Lbit value of the CHI register or an Lbit value of the Temp. Result based on the bit value of the merge mask corresponding to the Lbit position.

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Ft. Collins, CO, United States of America

Stephen L Bass