Tela Innovations, Inc.

Stephen Kornachuk

Scott T Becker

Carole Lambert

Jim Mali

Brian Reed

James Mali

Joseph N Hong

A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. At least one irregular wire is formed within the given chip level and within a region bounded by the plurality of regular wires. Each irregular wire has a linear-shape with a length extending in the first direction and a width extending in the second direction. A distance as measured in the second direction between lengthwise centerlines of any irregular wire and any regular wire is not equal to an integer multiple of the fixed pitch.

Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

Enforcement of semiconductor structure regularity for localized transistors and interconnect

Within a dynamic array architecture, an irregular wire layout region within a portion of a chip level layout is bracketed by placing first and second regular wire layout shapes on a first and second sides, respectively, of the irregular wire layout region. One or more irregular wire layout shapes are placed within the irregular wire layout region. A first edge spacing is maintained between the first regular wire layout shape and a first outer irregular wire layout shape within the irregular wire layout region nearest to the first regular wire layout shape. A second edge spacing is maintained between the second regular wire layout shape and a second outer irregular wire layout shape within the irregular wire layout region nearest to the second regular wire layout shape. The first and second edge spacings are defined to optimize lithography of the regular and irregular wire layout shapes.

Optimizing layout of irregular structures in regular layout context

First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

Methods for defining contact grid in dynamic array architecture

A computer memory includes a primary self-timing signal path defined by a model wordline signal path and a model bitline signal pair path. The primary self-timing signal path is defined to generate and transmit a model bitline signal pair. The computer memory also includes a control block defined to receive the model bitline signal pair from the primary self-timing signal path. The control block is defined to sense when a distinctive differential exists between the signals of the model bitline signal pair. The control block is further defined to generate and transmit a sense enable signal to a memory core upon sensing the distinctive differential between the signals of the model bitline signal pair.

Memory timing apparatus and associated methods

A computer memory includes a sense enable control module for generating a sense enable signal for a memory core. The sense enable control module includes an active side for transmitting the sense enable signal for the memory core, and a calibration side for determining when the sense enable signal is to be transmitted by the active side. Both the active side and the calibration side are defined to receive a timing signal. The active side is defined to transmit a delayed version of the timing signal as the sense enable signal for the memory core. The calibration side is defined to adjust the delay amount associated with the delayed version of the timing signal to be transmitted by the active side based on a determined sufficiency of the delay amount.

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Stephen Kornachuk