Intel Corporation

Stephen Kim

Muhammad M Khellah

Anupama Ambardar Thaploo

Pascal Meinerzhagen

James W Tschanz

Frank Patrick O'Mahony

Rinkle Jain

Ajay Balankutty

Jihwan Kim

Yi-Chun Shih

Sandipan Kundu

Bong Chan Kim

Kaushik Mazumdar

Kai Yu

Vivek K De

Sriram R Vangal

Krishnan Ravichandran

Iqbal Rajwani

Minki Cho

Pascal A Meinerzhagen

Lei Jiang

Sunghyun Park

Yutao Liu

Dongmin Yoon

Suphachai Chai Sutanthavibul

Surya Sasi Kiran Tallapragada

Gurmukh Singh

Daivik H Bhatt

Richard Packard

A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

Wide-range inductor-based delay-cell and area efficient termination switch control

An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.

Active inductor based high-bandwidth 2-state 4-way data serialization apparatus and method

Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.

Reliable digital low dropout voltage regulator

An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.

Apparatus for data retention and supply noise mitigation using clamps

Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

Power switching circuitry including power-up control

Some embodiments include apparatuses and methods having a power switching unit to receive a first voltage and provide a second voltage having a value based on a value of the first voltage, a first loop to provide digital control information to control a switching of the power switching unit in order to maintain a relationship between the value of the second voltage and a value of a reference voltage, and a second loop coupled to the power switching unit and the first loop to calculate a value of energy consumption of at least a portion of the apparatus based at least on the digital control information.

Digital low drop-out voltage controller including embedded dual-loop feedback for minimum energy point operation

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Hillsboro, OR, United States of America

Stephen Kim