Logicvision, Inc.

Northern Telecom Limited

Mentor Graphics Corporation

Siemens Industry Software Gmbh

Stephen Kenneth Sunter

Aubin P J Roy

Benoit Nadeau-Dostie

Mark Hanson

Dwayne M Burek

Michael Howells

Go Simon Sunatori

Tina Najibi

Lawrence H Sasaki

Ronald G Wellard

Martin J Bell

Philip S Wilcox

Givargis Avareh Danialy

Stephen V Pateras

Walter H Banzhaf

Pièrre Gauthier

Abu S Hassan

Naveena Nagi

Yachin Afek

Nicholas Tsiakas

Charles Mc Donald

Nayan Mehta

Aspects of the disclosed technology relate to techniques of activity coverage assessment. Transistor-level circuit simulation is performed for a circuit design under a set of test stimuli, which determines values of one or more electrical properties for each of circuit elements of interest in the circuit design. The one or more electrical properties are selected based on information of the each of circuit elements of interest, which comprises what circuit element type the each of circuit elements of interest belongs to. Based on the values of the one or more electrical properties, activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli is determined.

Activity coverage assessment of circuit designs under test stimuli

This application discloses a computing system to identify multiple views of cells in a circuit design for selective utilization during analog fault simulation of the circuit design. The views of the cells can include two or more of macromodel design views, schematic design views, or extracted design views that includes parasitic elements extracted from a physical layout of the circuit design. The computing system can prompt generation of multiple netlists, each netlist generated based on a different combination of the identified views of the cells in the circuit design, or a list of macromodels with pin accurate subcircuit wrappers, parse and organize the cells in each netlist or the list of macromodels, identify one of the cells to inject with a defect, and selectively simulate portions from a plurality of the netlists based, at least in part, on the identified one of the cells to inject with the defect.

Analog fault simulation control with multiple circuit representations

Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated.

Defect injection for transistor-level fault simulation

Various aspects of the present invention relate to techniques of measuring delays between edges of signals of a circuit. Alternating signals, synchronous to a first clock, are supplied to a plurality of nodes of the circuit. First samples of a plurality of signals associated with the alternating signals are captured using a first capture clock, of which sampling instants are synchronous to a second clock. Second samples of the first samples are then captured using a second capture clock, of which sampling instants are also synchronous to the second clock. The captured second samples are conveyed via a shift register to a plurality of modulo counters. The measured signal delay includes a timing skew associated with the first clock and a timing skew of the first capture clock but not a timing skew of the second capture clock.

Circuit and method for measuring delays between edges of signals of a circuit

A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple paths, and may be implemented in digital boundary scan to test I/O pin delays. Synchronous to a first frequency, the circuit applies an alternating signal to the paths and samples the paths' output logic values synchronous with a second frequency that is asynchronous and coherent to the first clock frequency. The shift register conveys the samples to a modulo counter that counts the number of samples between consecutive rising or consecutive falling edges in the signal samples from a selected path. Between the two edges, the path or a path characteristic is changed, and the resulting modulo count after the second edge is proportional to the change in delay. The circuit can compare the count, or the difference between counts, to test limits.

Circuit and method for simultaneously measuring multiple changes in delay

A method and circuit for measuring a time interval between transitions of periodic signals at nodes of a circuit-under-test (CUT), the signals having a periodic clock frequency, the method includes periodically latching a digital value of a first periodic signal at edges of an undersampling clock, simultaneously periodically latching a digital value of a second periodic signal at edges of the undersampling clock, combining the latched digital values of the first and second periodic signals to produce a combined output whose duty cycle is proportional to the time interval between a median edge of latched digital values of the first periodic signal and a median edge of latched digital values of the second periodic signal; and counting the number of undersampling clock cycles in which the combined output is a predetermined logic value within a predetermined time interval whereat the number is proportional to a time interval between a transition of the first periodic signal and a transition of the second periodic signal.

Circuit and method for measuring delay of high speed signals

A circuit and a method are provided for testing the enable function of Boundary Scan Register bits that control the driver of unconnected I/O pins of an 1149.1-compliant IC during the IC's reduced pin-count access manufacturing test, and to test the connections to these pins during the test of a circuit board containing the IC, without causing excessive current if a pin is inadvertently short circuited.

Boundary scan with strobed pad driver enable

A boundary scan cell for use in a circuit having a boundary scan shift register (BSSR) having boundary scan cells associated with pins of the circuit, the cell having a single-bit shift register element and an associated update latch, comprises a logic circuit for controlling the logic state of an associated pin, analog switches connecting the associated pin to analog test buses, and logic circuitry for selectively configuring the cell in a parametric test mode in which the cell shift register element controls the analog switches, and in a digital test mode in which the cell shift register element controls the logic state of the associated pin.

Circuit and method for adding parametric test capability to digital boundary scan

A method and circuit for measuring a statistical value of jitter for a data signal having a data rate f, comprises digitally sampling the data signal at a sampling rate, f, to produce sampled logic values, where f/fis a predetermined non-integer ratio; and analyzing the sampled values to deduce a statistical value of the jitter.

Circuit and method for measuring jitter of high speed signals

A software and hardware system and an associated methodology provides ATE-independent go/no-go testing as well as advanced failure diagnosis of integrated circuits for silicon debug, process characterization, production (volume) testing, and system diagnosis comprises an embedded test architecture designed within an integrated circuit; means for seamlessly transferring information between the integrated circuit and its external environment; and an external environment that effectuates the seamless transfer for the user to perform relevant test and diagnosis.

Method, system and program product for testing and/or diagnosing circuits using embedded test controller access data

A circuit and method are described in which a DC voltage or current is connected to a high frequency, AC-coupled signal path between a transmitter and a receiver, and the bit error rate of the data transmission is tested while applying an altered bias voltage to the received signal. The bias voltage can be connected via a resistor, inductor or transistors. The transmitted signal is attenuated resistively, and a load capacitance is applied whose value causes digital transition times to exceed one unit interval. An intended application is testing of an integrated circuit, serializer/deserializer (serdes) operating above 1 GHz.

Circuit and method for testing high speed data circuits

A method for accurately delivering a voltage to a circuit node of an integrated circuit having analog buses and transmission gates selectively connecting the circuit node to the buses, comprises sensing the voltage on the circuit node via a first of the buses under control of a first periodic signal; applying a first stimulus voltage to the circuit node via a second bus under control of a second periodic signal; and applying a second stimulus voltage to the circuit node under control of a third periodic signal which is inverted with respect to the second periodic signal so that the circuit node is driven alternately to the first stimulus voltage and to the second stimulus voltage.

Circuit and method for accurately applying a voltage to a node of an integrated circuit

A method for testing an integrated circuit (IC) for open defects in a printed wire connected to an IC pin of the IC, the method includes measuring the capacitance of the IC pin; comparing the value of the measured capacitance to an expected IC pin capacitance value for the pin unconnected, and determining that an open defect exists proximate the pin when the measured capacitance is less than a predetermined value based on the expected IC pin capacitance value.

Circuit and method for determining the location of defect in a circuit

A sampling circuit for use in testing an analog waveform includes a sampling switch for sampling an analog waveform, a sample storage capacitance including a single capacitance and a plurality of capacitances selectably connected in parallel; and a sampling pulse generating circuit.

Method and circuit for testing high frequency mixed signal circuits with low frequency signals

A method for sequentially accessing circuit nodes in an IEEE 1149.4 compatible mixed-signal circuit having a test access port controller, a boundary scan register having a boundary module associated with each circuit node, analog busses for accessing the circuit nodes and connecting the analog bus pins and each boundary module, the boundary modules having analog switches for selectively accessing the busses, shift register elements and associated update latches for controlling the analog switches, the method comprising initializing the boundary modules with logic values including an analog switch enabling logic value for enabling a switch associated with a first of the circuit nodes and enabling the switch; monitoring or driving the first signal node via the analog busses; suppressing capture mode in each boundary module; and for each additional circuit node to be accessed, shifting the switch enabling logic value from the boundary module containing the logic value to the boundary module associated with the next signal node to be accessed, enabling a switch associated therewith; and monitoring or driving the next signal node via the analog bus.

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Nepean, Canada

Stephen Kenneth Sunter