Texas Instruments Corporation

Stephen Keith Heinrich-Barna

Saim Ahmad Qidwai

Raviprakash Suryanarayana Rao

Srinath Mathur Ramaswamy

Clive D Bittlestone

Alwin J Tsao

Douglas P Verret

Joyce Kwong

Chiraag Juvekar

Aswin N Mehta

Clyde F Dunn

Robert Antonio Glazewski

Cetin Kaya

Sung-Wei Lin

John Howard MacPeak

John H Macpeak

William Francis Kraus

Jonathon Barry Miller

Robert Antoni Glazewski

A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbs

A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Memory circuit with leakage compensation

An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously.

Sense amplifier with offset compensation

An amplifier circuit is disclosed having an amplifier with first and second input terminals. The amplifier circuit includes a first compensation capacitor coupled to the first input terminal and having a first capacitance, a second compensation capacitor coupled to the second input terminal and having a second capacitance, a first transistor coupled between the first compensation capacitor and a reference voltage and having a gate terminal that receives a first control signal, and a second transistor coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal. The amplifier circuit includes a programmable latch circuit arranged to provide the first and second control signals, wherein the first and second transistors are of the same conductivity type, and the first control signal and the second control signal are complementary signals with respect to each other.

Read-only ('RO') data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory ('FRAM') array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

Method of manufacturing a dual mode ferroelectric random access memory (FRAM) having imprinted read-only (RO) data

An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits.

Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data

An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Well resistors and polysilicon resistors

A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.

FRAM cell with cross point access

One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

System and method for reading memory

Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist capacitor coupled to a discharge node coupled to a bit line. The write assist circuit further includes a transistor to receive an enable signal to couple the bit line to a low voltage rail. A voltage source is provided to charge the capacitor. The voltage produced by the voltage source is limited to limit the pull down voltage at the discharge node from the write assist capacitor.

Growing community of inventors

Murphy, TX, United States of America

Stephen Keith Heinrich-Barna