Toshiba Memory Corporation

Toshiba Corporation

Stephen K Pardoe

Nigel Rowe

A solid state drive (SSD) with power loss protection (PLP) and a method of PLP for an SSD is disclosed. In one embodiment, the SSD includes an SSD controller with one or more memory device controllers, a volatile memory in communication with the SSD controller, a non-volatile memory in communication with the SSD controller, and a power circuit in communication with the SSD controller and configured to supply power to the non-volatile memory during a normal operation of the SSD. The non-volatile memory includes a plurality of non-volatile memory devices arranged in a plurality of partitions that are controlled by the one or more memory device controllers. In the event of a power loss or failure, the power circuit supplies power to active partitions, which correspond to less than all of the plurality of partitions of the plurality of non-volatile memory devices.

Power loss protection for solid state drives

A solid state drive (SSD) with improved power efficiency includes one or more non-volatile memory devices configured to operate according to a programming voltage for a program function or an erase function and to a supply voltage for a read function. The SSD also includes a voltage regulator, external of the one or more non-volatile memory devices, having an output connected to the one or more non-volatile memory devices to supply the programming voltage and an input connected to receive a first voltage, the voltage regulator configured to convert the first voltage to the programming voltage. A discrete capacitor is connected to supply the first voltage to the voltage regulator. The one or more non-volatile memory devices operate according to the programming voltage supplied by the voltage regulator during both the normal operation of the SSD and in the event of a power loss or failure of the SSD.

Solid state drive with improved power efficiency

Methods of manufacturing circuit boards and circuit boards formed thereby to have a surface that is configured to receive circuitry and a notch of a selectable configuration in a lateral edge along the surface of the circuit board boards, and where the selectable configuration is configured to convey identifying information relating to the circuit boards. Such a circuit board can be produced from a panel containing one or more circuit boards, wherein at least one circuit board has a border adjoined and defined by a partition feature that is configured to enable the circuit board to be physically separated from other portions of the panel. Notches having the same of varying selectable configurations may be formed on the at least one circuit board during the manufacturing of the circuit board.

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Swindon, United Kingdom

Stephen K Pardoe