Sun Microsystems, Inc.

Stephen K Howell

Robert Yung

Daniel S Rice

Liang He

Peter Farkas

Jaijiv Prabhakaran

A parallel processor which is capable of partitioned multiplication and partitioned addition operations convolves multiple pixels in parallel. The parallel processor includes a load and store pipeline of a load and store unit which retrieves data from and stores data to memory and one or more arithmetic processing pipelines of an arithmetic processing unit which aligns data and performs partitioned multiplication and partitioned addition operations. A patch of pixels from a source image are convolved substantially simultaneously in the arithmetic processing pipeline of the processor by execution of the partitioned multiplication and partitioned addition operations. At substantially the same time, a subsequent patch of pixels from the source image are read by the load and store unit of the processor. The subsequent patch of the source image is a patch which is aligned with respect to a secondary index and is incremented along a primary index to avoid excessive cache misses when retrieving pixel data for convolution. Reading of pixel data is performed in the load and store pipeline of the processor while the arithmetic processing pipeline substantially simultaneously performs partitioned arithmetic operations on the pixel data to thereby convolve the pixel data.

Graphical image convolution using multiple pipelines

An image rescaling method utilizing a parallel processor is provided. The computer-implemented method includes the steps of loading multiple word components into a processor in one machine instruction, each word component associated with a pixel of an image; rescaling the multiple word components in parallel; and packing the rescaled multiple word components into an image buffer in one machine instruction. Additionally, a second set of multiple word components may be processed concurrently with the processing of a first set of multiple word components.

Image rescaling in a parallel processor

In a processor, a method for performing table-lookup transformation through a look-up table a source image having a plurality of source pixels to derive a destination image having a plurality of destination pixels. The method includes the step of deriving, for each value in a source pixel of the plurality of source pixels, a look-up result. The aforementioned look-up result represents a value in a corresponding destination pixel of the plurality of destination pixels. The method further includes the steps of loading a plurality of the look-up results into a plurality of graphics registers in the processor and accumulating the plurality of the look-up results in the plurality of graphics registers into an accumulation register in the processor. Additionally, there is also provided the step of storing the accumulation register into the destination image.

Methods and apparatus for table lookup transformation of digital images

Image operations are implemented using a specially developed instruction set in a parallel processing environment that maximizes parallelization of operations. Graphics data partitioned addition and multiplication instructions allow for simultaneous addition or multiplication of multiple words of graphics data in parallel using a number of processing sub-units of a graphics execution unit.

Microprocessor with graphics capability for masking, aligning and

A computer system which includes a processor having an instruction set capable of 'delaying' block-store instructions related to any outstanding block-load instruction(s). Accordingly, a method for interleaving block data transfers and processing steps which exploits the characteristics of the instruction set and architecture of the processor in order to increase efficiency and throughput of the computer system is provided. Hence by interleaving the block-store instruction of the previous data block with the block-load instruction of the next data block, the entire block transfer process can streamlined.

Interleaving block operations employing an instruction set capable of

A system and method for a simultaneous multi-band block-stop filter is disclosed. The block-stop filter provides rapid filtering of an input data stream by simultaneously comparing a plurality of data band components to the low threshold, associated with the band of which the particular data band component is a member, and then simultaneously comparing the plurality of data band components to an associated high threshold. The block-stop filter can also improve performance by parallelizing the act of storing the filtered data band components into the output data stream.

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Santa Clara, CA, United States of America

Stephen K Howell