At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Teradyne, Inc.

Stephen K Eng

Joseph Elide Landry

Philip J Baun, Jr

Michael Francis McGoldrick

Joseph F Carriere

David A Milley

David C Rhodes

Jonghee Lee

William T Borroz

Thomas M Nolan

Michael F Mcgoldrick

A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.

Adjustable test pattern results latency

Protection switching of digital signal transmitting and receiving hardware is realized in a 'hitless' manner. The hitless switch is obtained by employing hardware switching units which can individually determine the instant to switch from an active state to a standby state and vice versa. A switch is initialized by supplying a switch request signal from a control unit to a hardware switching unit in the active state. The active hardware switching unit, upon detecting a prescribed bit condition, for example, a predetermined bit state, of the digital signal being supplied as an output therefrom, supplies a predetermined synchronization pulse to the standby hardware switching unit. In response to the synchronization pulse, the standby hardware switching unit forces the bit condition of a bit of the digital signal to be supplied as an output therefrom resulting from a current input bit to be in the same bit condition as that detected in the active hardware unit. Output circuits in both the active hardware switching unit and standby hardware switching unit are simultaneously turned OFF and ON, respectively, in the individual units by observing the digital signal being supplied as an input to both units. Upon detection of a predetermined bit condition of the input digital signal individually by each of the hardware switching units, the active unit output circuit is turned OFF and the standby unit output circuit is turned ON at the same instant. The instant of turning OFF and On of the output circuits is determined individually in each hardware switching unit.

Digital signal hardware protection switching

A channel bank unit for interfacing baseband user signals with a PCM carrier communications channel. The channel bank unit includes a circuit allowing verification of the transmission interity between the channel bank unit and external equipment having two-way communication with the channel bank unit. The circuit includes a first portion for evaluating the reception integrity of signals received from the external equipment and a second portion for imposing a parity sense on the signals transmitted to the external equipment that is related to the evaluation results of the first portion.

D-5 Channel bank control structure and controller

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Andover, MA, United States of America

Stephen K Eng