Pmc-sierra, Inc.

Stephen Julien Dabecki

Sivakumar Radhakrishnan

Charles Kevin Huscroft

Brian D Gerson

David Walden Wong

Vernon Robert Little

Maher Nihad Fahmi

Barry Benjamin Hagglund

David Wong

A ring interface is coupled to a current node in a ring network having a plurality of nodes and corresponding ring interface for each of said nodes. The ring interface includes a ring input port operative to conduct upstream message packets from a previous node to the ring interface, a ring output port operative to conduct message packets to a next node of the ring network, and a bypass queue operative to buffer message packets. A receive queue buffers message packets before passing them on to the current node. An address filter is coupled to the ring input port to receive the upstream message packets, read their destination addresses and pass them to the bypass queue if the addresses correspond to another node and pass them to the receive queue if their addresses are that of the current node. A transmit queue buffers message packets from the current node and a bypass-transmit queue arbiter is coupled to outputs of the bypass queue and the transmit queue and is operative to select message packets from one of the bypass queue and the transmit queue in accordance with predetermined selection criterion and transmits the selected message packets to the ring output port.

Ring interface and ring network bus flow control system

A method of determining an error detection code (EDC) on incoming data which includes a reserved bit field, comprising applying the incoming data to inputs of both an input data CRC (IDC) calculator and to an input data and reserved field CRC (IDRC) calculator, calculating the EDC on successive input data words and recursively updating the EDC in both the IDC and IDRC calculators, selecting a payload of the input data as a system output signal for all payload words, and subsequently selecting a output EDC word from the IDRC calculator in a time immediately following a final payload word which contains the reserved field.

High speed cyclic redundancy check algorithm

According to the invention there is provided a method of signal coding that permits high speed data transmission over multiple pairs of UTP-5 cable from a transmission end to a receiving end which includes, at the transmission end, separating an incoming frame of data into a plurality of byte streams with a predefined sequence of bytes assigned to each of the streams, encoding every 2 bits of data in each stream into one of 4 logical voltage levels forming a symbol or quat thereby reducing the symbol or baud rate by 50% and inserting an escape sequence into one or more of the streams consisting of a sequence of zero's followed by a control code to indicate a transition from one state to another. At a receiving end, the method further includes reading the escape sequence and decoding the signals in accordance with the code contained in the escape sequence.

Line coding technique for efficient transmission and delineation of

An available bit rate scheduler for asynchronous transfer mode communication of a plurality of cells over a communication network in which each cell is characterized by a virtual circuit communication channel and in which each virtual circuit is characterized by one or more profiles. Each profile has a group of sub-profiles, with each sub-profile having a unique bandwidth allocation component. The scheduler incorporates a profile queue buffer for receiving, pairing and storing the profiles and sub-profiles and, a link list processor coupled to the profile queue buffer to receive the profile, sub-profile pairs. The link list processor detects null profile, sub-profile pairs in the buffer and, over-write them with a selected one of the virtual circuit profile, sub-profile pairs. A valid pending register of length p bits, and a memory are coupled to the link list processor. The memory stores pointers to link lists of virtual circuits associated with each of the profile, sub-profile pairs received by the link list processor. The pointers comprise, for each of the link lists, a head pointer to a first entry in the link list and a next pointer to a virtual circuit in the link list last associated by the link list processor with one of the profile, sub-profile pairs.

Enhanced integrated rate based available bit rate scheduler

A method of scheduling cell transmission over an asynchronous transfer mode communication channel. The channel has a characteristic transmission rate that is related to the system clock frequency .function. and an allowed cell rate ACR expressed as a floating point number having a mantissa m, and an exponent e, where 0.ltoreq.m.ltoreq.511, 0.ltoreq.e.ltoreq.31 and ACR=(1+m/512)*2.sup.e. If m.gtoreq.128 then the reciprocal of the mantissa portion (1+m/512) is evaluated by piece-wise linear approximation of the function: ##EQU1## Otherwise, if m&lt;128 then the mantissa portion is evaluated by piece-wise linear approximation of the function: ##EQU2## A selected cell is then scheduled for transmission at a time T relative to the transmission time T.sub.0 of a cell transmitted immediately prior to the selected cell, where T=T.sub.0 +(ACR.sup.-1)*f. A hardware embodiment of the invention, requiring only one 9-bit two's complementer, three 11-bit adders, and glue logic for multiplexing/control is easily implemented using VLSI circuitry in compliance with ATM Forum traffic management standards, without resort to hardware division or multiplication.

Allowed cell rate reciprocal approximation in rate-based available bit

An available bit rate scheduling method and apparatus for asynchronous transfer mode communication of a plurality of cells over a network characterized by a system clock frequency f and an allowed cell rate ACR. Each cell belongs to an assigned virtual circuit communication channel which is defined by a set of negotiated traffic parameters. The invention partitions the ACR's of the virtual circuits into a smaller subset of profiles/sub-profiles and conducts a deterministic search to service them. The scheduler incorporates a profile generator for iteratively generating a number p of the profiles by (i) outputting a k*modulo 2.sup.i th one of the profiles during each kth iteration of the profile generator, where 1.ltoreq.i.ltoreq.p and 1.ltoreq.k.ltoreq.p-1; (ii) outputting a null profile during each 2.sup.p th one of the iterations; and, (iii) dispatching the profiles from the profile generator to the profile queue such that a particular profile is dispatched at a time T=T.sub.0 +(1/ACR)*f, where T.sub.0 is the dispatch time of a profile dispatched immediately prior to the particular profile. A profile queue coupled to the profile generator receives and sequentially stores the generated profiles. A virtual circuit processor sequentially receives the profiles from the profile queue and, for each one of the received profiles, dispatches to an output queue all virtual circuits which are characterized by the one received profile.

Growing community of inventors

Maple Ridge, Canada

Stephen Julien Dabecki