International Business Machines Corporation

Stephen Joseph Schwinn

Matthew Ray Tubbs

Ronald Nick Kalla

Richard William Doing

Gordon Clyde Fossum

Charles David Wait

Edward John Silha

Kenichi Tsuchiya

Van Hoa Lee

Mark Joseph Hickey

Charles Andrew McLaughlin

A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In particular, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or more latches that are intermediate to such pipeline stages to a transparent state such that the output of the pipeline stage preceding such latches is passed to the subsequent pipeline stage during the same clock cycle so that both such pipeline stages effectively perform steps for the same instruction during each clock cycle. Then, with the selected pipeline stages merged, the power consumption of the execution pipeline can be reduced (e.g., by reducing the clock frequency and/or operating voltage of the execution pipeline), often with minimal adverse impact on performance.

Dynamic merging of pipeline stages in an execution pipeline to reduce power consumption

A circuit arrangement and method utilize a plurality of execution units having different power and performance characteristics and capabilities within a multithreaded processor core, and selectively route instructions having different performance requirements to different execution units based upon those performance requirements. As such, instructions that have high performance requirements, such as instructions associated with primary tasks or time sensitive tasks, can be routed to a higher performance execution unit to maximize performance when executing those instructions, while instructions that have low performance requirements, such as instructions associated with background tasks or non-time sensitive tasks, can be routed to a reduced power execution unit to reduce the power consumption (and associated heat generation) associated with executing those instructions.

Structural power reduction in multithreaded processor

The invention includes receiving a first instruction in an in-order execution processing pipeline; starting execution of the first instruction; determining a first set of internal operation bits indicating a prospective value of control bits upon complete execution of the first instruction; determining whether the first instruction is a committed instruction; receiving a second instruction in the in-order execution processing pipeline before execution of the first instruction completes; determining a second set of internal operation bits based on: a) the first set of internal operation bits if the first instruction is a committed instruction; or b) a set of internal operation bits of a last committed instruction if the first instruction is not a committed instruction; and starting execution of the second instruction in the in-order execution processing pipeline before execution of the first instruction completes using the second internal operation bits. Numerous other aspects are provided.

Pipelined processing

A circuit arrangement and method utilize thread pair context caching, where a pair of hardware threads in a multithreaded processor, which are each capable of executing a process, are effectively paired together, at least temporarily, to perform context switching operations such as context save and/or load operations in advance of context switches performed in one or more of such paired hardware threads. By doing so, the overall latency of a context switch, where both the context for a process being switched from must be saved, and the context for the process being switched to must be loaded, may be reduced.

Pre-loading context states by inactive hardware thread in advance of context switch

An approach to optimize specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the 'intensity instruction' retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process. In one embodiment, the invention may be implemented using PowerPC&#x2122; assembly and VMX&#x2122; or Altivec&#x2122; instructions. In this embodiment, the intensity instruction may be represented as a 'vspecefp' instruction, which stands for a &#x201c;vector specular estimate floating point&#x201d; instruction.

Optimized specular highlight generation

A method for optimized specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the 'intensity instruction' retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process.

A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.

Method and apparatus for implementing power of two floating point estimation

A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.

Apparatus for supporting a logically partitioned computer system

A method, apparatus, and computer instructions for testing hardware in a data processing system having multiple partitions. A monitor process in a first partition assigned to a first processor is initialized. A random code generation process in a second partition associated with a second processor is initialized. The random code generation process generates instructions and executes the instructions to test the second processor. The monitor process monitors the random code generation process and resets the second processor if the random code generation process fails.

Method and apparatus for verifying hardware implementation of a processor architecture in a logically partitioned data processing system

A real address range check mechanism verifies real addresses generated in a computer system which translates real addresses from effective addresses, some of the effective addresses being real addresses not requiring translation. The system has at least two operating modes. In one mode, the range checking mechanism generates an error signal responsive to detecting a real address outside a predetermined range, and in the other operating mode no error signal is generated. Preferably, the computer system's hardware resources, including real address space, is logically partitioned, partitioning being managed by an ultra-privileged process called a hypervisor. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, real address range checking error signals being disabled in the hypervisor state.

Applications of operating mode dependent error signal generation upon real address range checking prior to translation

A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not. In the preferred embodiment, instruction addresses from either active or dormant threads can be pre-fetched in anticipation of execution. In the preferred embodiment, the processor supports different environments which use the hypervisor, supervisor and problem states differently.

Generating partition corresponding real address in partitioned mode supporting system

A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory containing real page numbers of the corresponding cache lines. A separate line fill sequencer exists for each thread. Preferably, the I-cache is N-way set associative, where N is the number of threads, and includes an effective-to-real address table (ERAT), containing pairs of effective and real page numbers. ERAT entries are accessed by hashing the effective address. The ERAT entry is then compared with the effective address of the desired instruction to verify an ERAT hit. The corresponding real page number is compared with a real page number in the directory array to verify a cache hit. Preferably, the line fill sequencer operates in response to a cache miss, where there is an ERAT hit. In this case, the full real address of the desired instruction can be constructed from the effective address and the ERAT, making it unnecessary to access slower address translation mechanisms for main memory. Because there is a separate line fill sequencer for each thread, threads are independently able to satisfy cache fill requests without waiting for each other. Additionally, because the I-cache index contains real page numbers, cache coherency is simplified. Furthermore, the ERAT avoids the need in many cases to access slower memory translation mechanisms. Finally, the n-way associative nature of the cache reduces thread contention.

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Lakeville, MN, United States of America

Stephen Joseph Schwinn