Arm Limited

Arm Limitied

Stephen John Hill

Glen Andrew Harris

Conrado Blasco Allue

David James Williamson

David John Butcher

Richard Slobodnik

Michael Peter Muller

Gerard Richard Williams

Stuart David Biles

Robert Campbell Aitken

Krisztian Flautner

David Hennah Mansell

Andrew Christopher Rose

Peter Richard Greenhalgh

Simon Andrew Ford

Vladimir Vasekin

Ganesh Suryanarayan Dasika

Rune Holm

Wilco Dijkstra

Hedley James Francis

A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.

Method and apparatus for tuning a processor to improve its performance

A data processing devicecomprises a plurality of storage circuits, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumerwith a number of lanes. The consumer is able to individually access each of the plurality of storage circuitsin order to receive into the laneseither a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumeris also able to execute a common instruction of each of the plurality of lanes. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuitsstores at most y bits of each of the data elements. Furthermore, each of the storage circuitsstores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuitscomprise no more than b/y storage circuits.

Data processing device and method for interleaved storage of data elements

A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units.

Data processing system

An integrated circuit includes an array of interconnected programmable logic elements () each logic element performing data processing control by a configuration. The logic elements may be part of a field programmable gate array. Embedded within the array are a plurality of dedicated communication interface circuits () providing access to one or more shared communication channels () to provide intra-array communication. Communication transactions between functional unit () are multiplexed (e.g. time-division-multiplexed) together to share a shared communication channel provided within the array.

Communication within an integrated circuit including an array of interconnected programmable logic elements

An integrated circuit () comprising an array () of interconnected configurable logic elements (), such as an FPGA array, is provided. The logic elements are used to form a power controller () which separately controls the power state of different regions of the array. Each region of the array contains one or more logic elements. Each region has a corresponding region controller () responsive to one or more power signals generated by the power controller to switch that region into the requested power state.

Power control of an integrated circuit including an array of interconnected configurable logic elements

A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit. Accordingly, this can significantly reduce the amount of logic duplicated in the decoder units which, in turn, reduces the amount chip area required to support decoding and reduces power consumption. Also, since the decode units are no longer required to support the decoding of such a high number of different instructions, the complexity of each decode unit can be reduced, which can result in increased performance during decode.

Multiple instruction set decoding

A data processing system is provided that includes an instruction decoderresponsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Compare and branch mechanism

An integrated circuitis formed of multiple layers of circuitssuperimposed to produce stacks of circuit blocks. Stack control circuitryis associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocksprovide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Integrated circuit with multiple layers of circuits

A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction.

Data processing apparatus and method for identifying sequences of instructions

A processoris provided with an instruction decoderwhich is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.

Null exception handling

A data processing system including multiple execution pipelines each having multiple execution stages E, E, Emay have instructions issued together in parallel despite a data dependency therebetween if it is detected that the result operand value for the older instruction will be generated in an execution stage prior to an execution stage which requires that result operand value as an input operand value to the younger instruction and accordingly cross-forwarding of the operand value is possible between the execution pipelines to resolve the data dependency.

Result bypassing to override a data hazard within a superscalar processor

A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed. This provides a particularly efficient mechanism for handling access requests in a variety of situations, for example within a virtualization environment where the access requests are directed to virtual devices implemented by hypervisor software.

Handling access requests in a data processing apparatus

Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided. The data processing apparatus comprises: decode/issue logic operable to receive and decode an instruction to be processed by the data processing apparatus and to determine when to issue a decoded instructions for execution by execution logic; execution logic operable to execute the decoded instructions; interface logic selectively operable to receive trace information relating to the state of the data processing apparatus generated in response to execution of the decoded instructions for transmission to trace monitoring infrastructure; and throttle logic operable to predict whether issuing the decoded instruction to the execution logic for execution would be likely to cause the trace information to be transmitted to said trace monitoring infrastructure to exceed a capacity of said trace monitoring infrastructure and, if so, to prevent the decode/issue logic from issuing the decoded instruction to the execution logic. Accordingly, the throttle logic reviews each instruction to be executed and predicts whether issuing that instruction at that time will or is likely to cause the capacity to be exceeded. In the event that the throttle logic determines that the capacity is likely to be exceeded, the instruction is prevented from being issued to the execution logic which reduces the likelihood that any state information is lost.

Preventing loss of traced information in a data processing apparatus

A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-processor register for storing configuration data and a respective debug register for storing debug data. A debug controller outputs debug data and co-ordinates debug operations. A configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units and a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. Separate provision of the debug ring-bus and the configuration ring-bus provides independent access to the co-processor register and to the debug register.

Provision of debug via a separate ring bus in a data processing apparatus

A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units. In the operational mode a configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units whereas a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. The first ring sequence is identical to the second ring sequence and the data processing apparatus is operable in the self-test mode to couple the configuration ring-bus and the debug ring-bus to provide a combined data path for communication of self-test data between the plurality of functional units.

Growing community of inventors

Austin, TX, United States of America

Stephen John Hill