Broadcom Corporation

Ultrasoc Technologies Limited

Avago Technologies International Sales Pte. Limited

Activated Content Corporation

Broadcom Europe Limited

Cambridge Silicon Radio Limited

Cambridge Consultants Limited

Avago Technologies Sales Pte. Limited

Alphamosaic Limited

Stephen John Barlow

Timothy James Ramsdale

David Plowman

Robert Swann

Neil Bailey

Andrew Brian Thomas Hopkins

James Andrew Hutchinson

Thomas Oscar Miller

Jack Stuart Haughton

Klaus Dieter McDonald-Maier

Roger Fane Sewell

Mark St John Owen

Arnab Banerjee

Simon Paul Long

James Digby Collier

Alistair Guy Morfey

Martin Whitfield

Andrew James Bower

Nel Bailey

Constantine Krasic

An apparatus for stitching together multiple camera images to form a blended image having an output projection format. The apparatus is configured to convert each of the multiple camera images into the output projection format. It is configured to stitch together the converted images to form a single image. It is also configured to output the single image as the blended image having the output projection format.

Apparatus and method for stitching together multiple images

A data packer forma bit stream for forwarding values to memory. The bit stream includes the values and respective prefixes for identifying the values and the data packer is configured to insert the prefixes at predetermined boundaries in the bit stream, such that a prefix for identifying one value is inserted between bits that define a value identified by a preceding prefix. A data unpacker unpacks a bit stream that comprises values and respective prefixes for identifying those values that are located at predetermined boundaries in the bit stream, such that a prefix for identifying one value is inserted between bits that define a value identified by a preceding prefix. The data unpacker identifies a prefix at a predetermined boundary in the bit stream and determine, in dependence on that prefix and the predetermined boundaries, a location of the next prefix in the bit stream.

Apparatus and method for packing a bit stream

An image processing apparatus is provided that comprises an input configured to receive an image and a Laplacian generator configured to generate, from the image, a Laplacian pyramid that represents the image as a series of frames that contain different frequency components of the image. The image processing apparatus also comprises a compressor configured to compress the Laplacian pyramid for writing to memory.

Apparatus and method for generating a Laplacian pyramid

An apparatus for filtering multiple images so that they can be stitched together to form a blended image, the apparatus comprising a plurality of filters configured such that: (i) each filter is configured to process only images from the multiple images that will be non-overlapping with each other in the blended image; and (ii) images that will overlap with each other in the blended image are processed by different filters.

Hardware optimisation for generating 360&#xb0; images

An apparatus for combining multiple images to form a blended image, configured to identify regions of overlap: (i) in a first image and in a second image, corresponding to where those first and second images will overlap each other in the blended image; and (ii) in the first image and in a third image, corresponding to where those first and third images will overlap each other in the blended image, identify an image quality associated with each region of overlap, determine a gain for each image that, when applied to the image as a whole, will minimise a sum of: (i) a difference between the image qualities associated with the regions of overlap in the first and second images; and (ii) a difference between the image qualities associated with the regions of overlap in the first and third images and apply the respective gains to the first, second and third images.

Blending images

Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.

Debug architecture

An integrated circuit supports auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power supply voltage of the peripheral device received during power-up of the MMP chip, power-up of the peripheral circuitry, and/or dynamically while the MMP is powered-up. The auto-sense pad may adjust drive strength of at least one other pad, which may be an output pad or a bidirectional pad, integrated on the MMP chip may be configured to operate using the determined output voltage. A rise time and/or fall time of signals output by the MMP chip may be varied by the adjustment of the drive strength.

Drive strength adjustment through voltage auto-sense

A data processing apparatus having processing circuitry and debug circuitry is debugged by operating the processing circuitry to generate data. The debug circuitry is employed to generate trace elements indicative of the operation of the processing circuitry. Trace elements are caused to be output from the data processing apparatus over a communication bus capable of connecting a plurality of devices. The communication bus is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system. The passing of the trace elements onto the communication bus is controlled using an interface unit of the debug circuitry. The interface unit comprises a controller arranged to allow each of the interface unit and processing circuitry to be separate processing systems which can each independently control data interchange from the data processing apparatus.

Data processing apparatus and related methods of debugging processing circuitry

A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code.

Register file with separate registers for compiler code and low level code

Certain embodiments of the invention may be found in a method for integrated circuit supporting auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power supply voltage of the peripheral device received during power-up of the MMP chip, power-up of the peripheral circuitry, and/or dynamically while the MMP is powered-up. The auto-sense pad may adjust drive strength of at least one other pad, which may be an output pad or a bidirectional pad, integrated on the MMP chip may be configured to operate using the determined output voltage. A rise time and/or fall time of signals output by the MMP chip may be varied by the adjustment of the drive strength.

Method and system for an integrated circuit supporting auto-sense of voltage for drive strength adjustment

A method of debugging a multiple concurrent processes comprising: obtaining, from each process, a plurality of events that have been processed and, if no time information is associated with each event, associating time information therewith; causing a display to display the events such that an event that has occurred in a first portion of the display associated with a first process at a first time is aligned with an event in a second portion of the display associated with a second process that has occurred at a similar time to the first time. To be accompanied, when published, by FIG.of the drawings.

Method of debugging multiple processes

The invention comprises an encoder for encoding a stegotext and a decoder for decoding the encoded stegotext, the stegotext being generated by modulating the log power spectrogram of a covertext signal with at least one key, the or each key having been added or subtracted in the log domain to the covertext power spectrogram in accordance with the data of the watermark code with which the stegotext was generated, and the modulated power spectrogram having been returned into the original domain of the covertext. The decoder carries out Fast Fourier Transformation and rectangular polar conversion of the stegotext signal so as to transform the stegotext signal into the log power spectrogram domain; subtracts in the log power domain positive and negative multiples of the key or keys from blocks of the log power spectrogram and evaluates the probability of the results of such subtractions representing an unmodified block of covertext in accordance with a predetermined statistical model.

Growing community of inventors

Cambridge, United Kingdom

Stephen John Barlow