Ambiq Micro, Inc.

Fusion Micromedia Corporation

Vizionware, Inc.

Sitera, Inc.

Sifera, Inc.

Stephen James Sheafor

Donovan Scott Popps

Scott McLean Hanson

James Yuan Wei

Daniel Martin Cermak

Christophe J Chevallier

Eric Jonathan Deal

Mark A Baur

Bradford C Lincoln

David Cureton Baker

Kenneth William Egan

Roger David Serwy

Christopher Koerner

James J Remedi

Robert Sugar

Gregory T Chandler

Marc William Miller

Jonathan L Huie

Scott McLean

Jitendra K Budwal

Ted Beck

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Very low power microcontroller system

A microcontroller system that includes a central processing unit (CPU), a first system memory, a first peripheral module, and a DMA controller is disclosed. The DMA controller includes a DMA processor, a DMA memory, and a DMA interconnect. The DMA memory stores information associated with the DMA processor. The DMA processor receives a command from the CPU or a signal from a peripheral processor of the first peripheral module that a first data transfer is requested. The DMA processor receives first data from the first system memory or the first peripheral module. The DMA processor, based at least in part on the information stored in the DMA memory, transmits the first data to the first peripheral module or the first system memory, thereby sparing the CPU from managing the transferring of the first data.

Enhanced peripheral processing system to optimize power consumption

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

SRAM with error correction in retention mode

A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

Low power autonomous peripheral management

An energy consumption monitor for use in an electronic system comprising an integrated circuit such as a microcontroller. The monitor comprises a counter adapted to accumulate pulses developed by a charge source, each pulse indicative of the delivery of one unit of charge to a load circuit. A monitoring facility monitors the counter to develop an energy consumption record over time.

Method and apparatus for monitoring energy consumption

A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.

Counter/timer array for generation of complex patterns independent of software control

A clock calibrator for use in an electronic system comprising an integrated circuit such as a microcontroller. The clock calibrator embodies a frequency adjustment facility adapted dynamically to adjust the frequency of one or more high-frequency clock generators as a function of a lower-frequency reference clock.

Low power automatic calibration method for high frequency oscillators

A clock synchronizer adapted to synchronize reading a Timer that is clocked asynchronously to the system clock.

Low power asynchronous counters in a synchronous system

Growing community of inventors

Boulder, CO, United States of America

Stephen James Sheafor