Qorvo Us, Inc.

Infineon Technologies North America Corp.

Agere Systems Inc.

Rf Micro Devices (cayman Islands), Ltd.

Infineon Technologies Ag

Infineon Technologies LLC

Siemens Microelectronics Limited

Amalfi Semiconductor Corporation

Gec Plessey Semiconductor, Inc.

Stephen James Franck

Baker P Scott

George Adrian Maxim

Jonathan James Ashley

Razmik Karabed

James Arthur Bailey

James Wilson Rae

Thomas Blon

Michael F Zybura

Zabih Toosky

William G Bliss

Sasan Cyrusian

Elmar Bach

Sateh M Jalaleddine

Fritz Mistlberger

Chu Hsiung Ho

Stephen Christopher Terry

Ying Shi

Chong Woo

Hui Liu

Daniel Ho

Heinrich J Stockmanns

Michael A Ruegg

Padmmasini Desikan

Matthias Driller

Siegfried Hart

Jungmin Park

Ulrich Huewels

Xin Wang

Ranganathan Desikachari

Alireza Oskoui

Matthew Clapp

Ted V Burmas

Sriharsha Annadore

Dominik Margraf

Tom Biedka

A power amplifier using multi-path common-mode feedback loops for radio frequency linearization is disclosed. In one aspect, a complementary metal oxide semiconductor (CMOS) power amplifier containing cascoded n-type field effect transistors (NFETs) and cascoded p-type FETs (PFETs) may have a common-mode feedback network and provides bias voltages that are dynamically varying with the signal power to keep the output common-mode fixed around a half-supply level, while the small-signal and large-signal transconductances of the FET's are kept balanced. A further feedback network may be associated with the supply voltage to assist in providing a symmetrical supply signal. The symmetrical supply signal allows for supply variations without introducing distortion for the power amplifier stage.

Power amplifier using multi-path common-mode feedback loop

A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop or the over-voltage protection loop contribute to an over-current protection signal.

Power amplifier with protection loop

A protection circuit for an acoustic filter and/or a power amplifier is disclosed. In one aspect, the protection circuit includes a bidirectional coupler that helps secure a measurement of power at an antenna. The power measurement is compared to a threshold by a detector, and if the power measurement is above the threshold, a signal is sent that causes debiasing of a power amplifier stage, which reduces power levels of signals being amplified by the power amplifier stage and correspondingly lowers the power level going through a filter associated with the power amplifier stage. By lowering the power level going through the power amplifier stage and the filter, both elements are protected against over power conditions allowing functionality to be maintained.

Protection circuit for acoustic filter and power amplifier stage

A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Power amplifier system

Reduced flyback electrostatic discharge (ESD) surge protection is disclosed. An ESD protection circuit differentiates ESD events from normal power on based on supply rise time. During an ESD protection cycle, the ESD protection circuit briefly clamps a supply on an identified ESD edge to limit and protect an electronic device from high voltage and/or current. In some cases, a surge condition may occur as the ESD protection circuit becomes disabled, such as in the presence of a fast rise time power supply. When the power supply is also inductive, a flyback voltage overshoot at the sudden release of the ESD clamp can result in permanent over voltage-related device damage. An exemplary ESD protection circuit includes a controlled disable state which reduces or eliminates flyback during such a surge by gradually ramping down current from the ESD protection cycle.

Reduced flyback ESD surge protection

A power amplifier system having a power amplifier with a signal input and a signal output, bias circuitry coupled to the signal input, and a radio frequency (RF) peak detector having an input coupled to the signal output is disclosed. The RF peak detector is configured to generate a peak voltage signal. Temperature-compensated overvoltage protection circuitry coupled between an output of the RF peak detector and a control input of the bias circuitry is configured to respond to the peak voltage signal crossing over a predetermined peak voltage threshold and to provide an overvoltage protection control signal to cause the bias circuitry to adjust biasing for the power amplifier to reduce an overvoltage condition at the RF peak detector input.

A radio frequency switch made up of a plurality of switch cells coupled in series between a first node and a second node is disclosed. Each of the plurality of switch cells has a switch field-effect transistor (FET) having a switch drain terminal, a switch source terminal, a switch gate terminal, and a switch body terminal. A body bias network having a first body bias FET with a first drain terminal coupled to the switch body terminal includes a first cross-FET with a second drain terminal coupled to a first source terminal of the first bias body FET and a second source terminal coupled to the switch gate terminal. A second body bias FET has a third drain terminal coupled to the switch body terminal, and a second cross-FET has a fourth drain terminal coupled to a third source terminal of the second body bias FET.

Radio frequency switch

The present disclosure relates to a power amplifier (PA) system provided in a semiconductor device and having feed forward gain control. The PA system comprises a transmit path and control circuitry. The transmit path is configured to amplify an input radio frequency (RF) signal and comprises a first tank circuit and a PA stage. The control circuitry is configured to detect a power level associated with the input RF signal and control a first bias signal provided to the PA stage based on a first function of the power level and control a quality factor (Q) of the first tank circuit based on a second function of the power level.

Linear CMOS PA with low quiescent current and boosted maximum linear output power

A gate power control technique for a power amplifier (PA) provides practical improved efficiency at backed-off power levels. It can be applied to the main gate of the output stage of the PA, the cascode gate, or any combination thereof. Both voltage mode and current mode signal processing may be used. The gate power control can be implemented in both open-loop and closed-loop using AC and DC coupled drivers and output stages. It may further use one or more control ports in the radio frequency (RF) signal path.

Gate-based output power level control power amplifier

Power amplifier (PA), regardless of the process used for the manufacturing of its devices, suffers from a nonlinear output capacitance that has significant impact on various aspects of the PA performance. This output capacitance is dependent on the large output voltage swing. Accordingly a compensation capacitance is added at the output of the PA that has a behavior that is inverse respective of the output voltage of that of the output capacitance of the PA. Connecting the compensation capacitor in parallel to the PA output capacitance, results in a total capacitance that is the sum of the output capacitance and its compensation capacitance. The total output capacitance is therefore essentially stable throughout the output voltage swing.

Power amplifier having a nonlinear output capacitance equalization

A power amplifier (PA) using switched-bulk biasing to minimize the risk of output stage snapback effect is disclosed. An adaptive biasing of the output stage prevents device breakdown while accommodating large voltage swings. These protection techniques can be applied to all types of cascode configurations of a PA, including single-ended, differential, quadrature, segmented and any combination thereto.

Output stage of a power amplifier having a switched-bulk biasing and adaptive biasing

Achievement of robust stability of a power amplifier (PA) that allows the sharing of the ground between the driver stages and the output stage is shown. A controlled amount of negative feedback is used to neutralize the local positive feedback that results from the driver-to-output stage ground sharing in the signal path, for example, a radio frequency (RF) signal path. The solution keeps a strong drive and a good performance of the PA. Exemplary embodiments are shown for the PA positive feedback neutralization. A first embodiment uses a ground signal divider while another embodiment uses a ground signal divider weighting technique.

Ground partitioned power amplifier for stable operation

A power amplifier using a drain (collector) power control loop in which the feedback signal is an estimated output power level computed with a linear summation of the output sensed voltage and current. Both RF and baseband voltage and current sensing are possible, and voltage-mode or current-mode signal processing are feasible. This control loop technique is applicable to any means of drain power control circuits such as: supply regulators, DC-DC converters and others. Voltage error amplifiers can be used in conjunction with voltage feedback network, while current error amplifiers can be used with current feedback networks. Regulator sharing between different bands may be used as an area and cost reduction solution. The linear voltage and current summation driven power control technique can be also applied to the gate (base) power control scheme. Similarly, voltage-mode and current-mode signal processing can be implemented.

Power amplifier with power feedback

Various voltage regulators and/or voltage regulation systems are disclosed. For example, a voltage regulation system that includes a source follower output is disclosed. The source follower output includes a transistor where the source of the transistor provides a baseline voltage to a regulated voltage output node. The voltage regulation system further includes a body damping circuit and a low speed feedback circuit. The body damping circuit is electrically coupled to the body of the transistor, and is operable to provide a rapid opposition to any voltage disturbance at the regulated voltage output node. The low speed feedback circuit is electrically coupled to the gate of the transistor, and is operable to return the regulated voltage output node to the baseline voltage.

Linear voltage regulator with improved large transient response

Growing community of inventors

Felton, CA, United States of America

Stephen James Franck