Northrop Grumman Systems Corporation

Stephen J Sarkozy

Richard Lai

Yaochung Chen

William Roland Deal

Xiaobing Mei

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.

Wrap around gate field effect transistor (WAGFET)

An integrated circuit comprising a substrate including a top-side surface and a backside surface and a plurality of circuit components fabricated on the top-side surface of the substrate. The circuit includes a plurality of electrically conductive vias extending into the substrate from the backside surface of the substrate. Some of the plurality of vias are through vias that extend completely through the substrate and make electrical contact with a circuit component on the top-side surface of the substrate and some of the plurality of vias are part-way through vias that extend only part-way through the substrate and are positioned directly opposite to a circuit component on the top-side surface of the substrate, where the part-way through vias extend at least half-way through the substrate. The number of part-way through vias is determined based on the number of part-way through vias that are necessary to suppress substrate modes in the substrate.

Growing community of inventors

Redondo Beach, CA, United States of America

Stephen J Sarkozy