International Business Machines Corporation

Stephen J Nadas

Raymond J Pedersen

Ronald F Hill

Donald W McCauley

James R Robinson

Robert J Bullions, Iii

A method and system for controlling references to system storage. Milli-code mode provides a flexible technique for overriding storage controls associated with referencing system storage of a data processing system. The storage controls to be overridden are not replaced and therefore, a restore of the previous contents of those controls is not necessary. This allows for an increase in system performance and an increase in the efficiency and flexibility of the system. In addition to the above, a system request instruction is provided, which enables flexibility in the manner in which system requests are executed. The flexibility of the system request instruction reduces the number of instructions needed to perform system requests.

Method and system for controlling references to system storage by

A hardware controlled pipelined processor having an interpretive storage and multiple execution units employs interpretive storage 'milli-instructions' and an interpretive execution 'milli-mode'. Additional hardware controlled instructions that are exclusively used in milli-mode may be added to provide additional controls or to improve performance (they augment the architected instruction set). Milli-mode routines intermingle milli-mode only instructions with architected instructions to implement complex functions. One milli-instruction called the DRAIN INSTRUCTION PIPELINE (DIP) causes the pipeline to drain selectively so the milli-programmer determines when and and what type of pipeline drain to perform. A DRAIN INSTRUCTION PIPELINE causes suspension of decoding until a selected event occurs. This DIP instruction includes options for suspending decoding until one of the following events have occurred: 1. all conceptually previous macro-instructions have completed; 2. all conceptually previous instructions have completed; 3. all store requests have reached the point where no exceptions would occur, but the actual store may not have completed; 4. all conceptually previous stores from all conceptually previous units-of-operation have competed (serialize); or 5. invalidate instruction buffers and fetch the next sequential macro-instructions.

Computer system permitting switching between architected and

An alternate instruction architecture which uses the preexisting dataflow and hardware controlled execution units of an otherwise conventional pipelined processor to accomplish complex functions. Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These milli-mode instructions augment the standard 'user visible' architected instruction set (which in the preferred embodiment is the System 390 instruction set). Millicode routines can intermingle the milli-mode only instructions with standard system instructions to implement complex functions. The set of instructions available in milli-mode can be considered to be an alternate architecture that the processor can execute. The millicode and standard system architectures each have there own set of architected registers. However, these registers are dynamically taken from and returned to a common physical register pool under control of a register management system. Provision is also made for communication between the two architectures such that data in the milli-registers and the standard architected registers (such as GPRs) can be exchanged. A set of register operand registers is provided to enable explicit updates of general purpose registers from millicoded routines. Both milli-instructions and standard architecture instructions can be present in the pipeline simultaneously. Provision is thus also made for performing a controlled pipeline reset of the facilities manipulated by the two types of architectures.

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Poughkeepsie, NY, United States of America

Stephen J Nadas