Harris Corporation

Stephen J Glica

Harold Allen Wittlinger

Salomon Vulih

Raymond L Giordano

John A Olmstead

In systems embodying the invention, circuitry responsive to first and second, complementary, input signals controls the application of the input signals to a positive signal integrator and to a negative signal integrator. When the amplitude of the input signals is greater than a predetermined value, the one of the two input signals which is positive relative to the other is applied to the positive signal integrator and the other one of the two input signals is applied to the negative signal integrator. When the amplitude of the input signals is smaller than a predetermined level, the circuitry causes the periodic application of the first input signal to the positive signal integrator and the second input signal to the negative signal integrator during one time interval, and the periodic application of the first input signal to the negative signal integrator and the second input signal to the positive signal integrator during a second, subsequent, time interval of similar duration as the one time interval.

Electrical system with small signal suppression circuitry

Signals generated by a knock sensor are coupled to an electronic network for amplifying and processing the output signals of the knock sensor. The electronic network includes a device for charging a storage capacitor to a potential which is a function of the amplitude of the knock sensor output signal. The storage capacitor is coupled to the input of an amplifier via a normally closed first switch. A detector for sensing any disconnection of the knock sensor from the electronic system produces a control signal indicative of a disconnect condition. The control signal is used to open the normally closed first switch and to cause the input of the amplifier to be clamped to a reference potential which lies outside the signal range normally produced across the storage capacitor whereby the output of the output of the amplifier is placed at a predetermined level indicative of a disconnect condition. The amplifier thus produces signals at its output which are within a predetermined range during normal operation and a signal outside of this range in response to a knock sensor disconnect condition. Thus, a single line from the output amplifier carries regular normal signals and the disconnect signal lying outside the range of the normal signals.

Knock sensor system for detecting and responding to a disconnect

A comparator circuit has first and second inputs and an output and includes means for operating the comparator in alternate autozero and comparator phases. During an autozero phase, the inputs of the comparator are clamped to a reference potential and during a compare phase, input signals are applied to the input of the comparator. Control signals are applied to the inputs of the comparator during a portion of the compare phase. The control signals determine the state of the comparator output when the input signals applied to the inputs of the comparator are below a predetermined level.

Comparator with small signal suppression circuitry

A first IGFET and a first bipolar transistor are connected in series between a first power terminaland a first load terminal. A second IGFET and a second bipolar transistor are connected in series between a second load terminal and a second power terminal. the first and second IGFETs are biased to pass the same load current. The first and second bipolar transistors are selectively turned on at the same time to permit current flow via a load which may be connected between the first and second terminals. When the first and second bipolar transistors are turned-off, they prevent conduction (except for leakage) between the load terminals and the first and second power terminals, if and when the voltage at the load terminal goes positive and/or negative. The circuit also includes means for compensating for the base current of the first and second bipolar transistors.

BIMOS current driver circuit

A comparator circuit includes first and second differential amplifier input stages to which are applied the same differential input signals with each stage being powered by first (V1) and second (V2) operating potentials. The first stage is only responsive to differential input signals ranging in value between V1 and a first state threshold voltage (V.sub.T1) above V2. The second state is only responsive to differential input signals ranging in value between V2 and a second state threshold (V.sub.T2) below V1. Each one of the first and second stages, when operative, produces output signals which can swing fully between V1 and V2 as a function of the input signals. The output signals of the first and second stages are combined in an OR'ing circuit to produce an output signal whose amplitude can swing over the full operating voltage applied to the first and second supply lines for values of differential input signals ranging between V1 and V2.

Full range input/output comparator

A power-on reset circuit produces a momentary signal when the operating potential increases above a first threshold and when the operating potential decreases below a second threshold level. In a preferred embodiment, the circuit includes first and second IGFETs of first conductivity having their conduction paths connected in series between a positive operating terminal and a first node and third and fourth IGFETs of second conductivity having their conduction paths connected in series between the first node and a negative operating terminal. An inverter is connected at its input to the first node. The output of the inverter is coupled via a first feedback network to the intersection of the conduction paths of the third and fourth IGFETs to control the voltage level at which the third IGFET conducts when power ramps up. The output of the inverter is also coupled via a second feedback network to the intersection of the conduction paths of the first and second IGFETs to control the voltage level at which the second IGFET conducts when power ramps down.

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Somerset, NJ, United States of America

Stephen J Glica