Texas Instruments Corporation

Stephen (Hsiao Yi) Li

Jonathan L Rowlands

Frank L Laczko, Sr

Maria B H Gill

Fuk Ho Pius Ng

Paul M Look

Dong-Seok Youm

David (Shiu) W Kam

A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction registerreceives an instruction for execution. Decoding circuitryselects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexorto form an address which can be used to access a data value or to form a target address for a branch instruction. Mux controlparses the immediate value to determine how to combine the immediate value and the index value.

Data processing device with an indexed immediate addressing mode

A data processing device uses a portion of a random access memory as an input buffer for holding a portion of a stream of data which is being processed by a processing unit within the processing device. Various break-point source tasksdetermine discontinuities in the portion of data stored in the input buffer and a sorted list of the addresses of the discontinuities is maintained in breakpoint queue. Since the buffer is managed in a FIFO manner, a single breakpoint registeris sufficient to monitor addresses as they are provided by an address registerfor accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task

Input/output buffer managed by sorted breakpoint hardware/software

A data processing device uses a portion of a random access memory as an output buffer for holding a frame of PCM sample data which is being output after being processed by a processing unit within the processing device. Fine grained synchronization between a reference clock and a stream of PCM data frames is provided by transferring only a portion of selected frame of PCM sample data PCM(n&plus;1), in response to a time difference,A breakpoint address is determined to delineate the portion of the selected frame that is to be transferred. A sorted list of the addresses of the discontinuities is maintained in breakpoint queue. Since the buffer is managed in a FIFO manner, a single breakpoint register is sufficient to monitor addresses as they are provided by an address register for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task

Fine-grained synchronization of a decompressed audio stream by skipping or repeating a variable number of samples from a frame

A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register,receives an instruction for execution. Decoding circuitry,selects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexor,to form an address which can be used to access a data value or to form a target address for a branch instruction. Mux control,parses the immediate value to determine how to combine the immediate value and the index value.

A data processing device is provided which has multiprocessors that can be configured on a cycle by cycle basis as loosely coupled or tightly coupled. Bit-stream Processing Unit (BPU),executes instructions from ROM,and accesses data from RAM,. Similarly, Arithmetic Unit (AU),executes instructions from ROM,and accesses data from RAM,. Both processor operate in parallel and exchange data by accessing RAM,. AU,can receive an instruction directive from BPU,directing it to perform a selected sequence of instructions in a loosely coupled manner. AU,can also receive an instruction directive from BPU,directing that a portion of AU,operationally replace a portion of BPU,for the duration of one instruction which allows data to be passed directly between the processors in a tightly coupled manner.

Microprocessor with functional units that can be selectively coupled

A data processing device uses a portion of a random access memory as an input buffer for holding a portion of a stream of data which is being processed by a processing unit within the processing device. Various break-point source tasks,determine discontinuities in the portion of data stored in the input buffer and a sorted list of the addresses of the discontinuities is maintained in breakpoint queue,. Since the buffer is managed in a FIFO manner, a single breakpoint register,is sufficient to monitor addresses as they are provided by an address register,for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task

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Garland, TX, United States of America

Stephen (Hsiao Yi) Li