Qlogic Corporation

Divicom Inc.

Stephen How

Rexford Alan Hill

William Clinton Terrell

Jean Kodama

Harun Muliadi

Tracy Edmonds

Eric Russell Peterson

Norman Chan

Michael Nishimura

Wayland Joeng

Brian W Johnson

Nolan Daines

Mike Perkins

Tom Ayers

Keith Vertrees

Emanuel Washington

A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction. The nonvirtual transaction accomplishes the intent of the virtual transaction but operates on an actual network port, for example, a storage device.

Router with routing processors and methods for virtualization

Router and methods for distributed virtualization

Router and methods using network addresses for virtualization

A transport stream decoder/demultiplexer is provided which includes a program clock recovery circuit for recovering a program clock from program clock reference (PCR) values contained in selected transport packets. A processor is provided for extracting elementary stream data from transport packets labeled with packet identification codes (PIDs) that are specified by a host processor. The processor separately stores the elementary stream data of each stream. A host processor interface is also provided for transferring data between an external host processor and the program clock recovery circuit. A memory manager may be provided for storing the data extracted by the processor for each elementary stream in a corresponding queue. The queues may be maintained by the memory manager in an external RAM. A descrambler interface may be provided for transferring scrambled data and data derived from conditional access information between the processor and an external descrambler. In addition, at least one elementary stream interface, such as a video interface or audio interface, may be provided for outputting extracted elementary stream data for a particular elementary stream from a corresponding queue. Furthermore, a high speed interface may be provided for outputting transport packet data prior to data extraction by the processor.

Transport stream decoder/demultiplexer for hierarchically organized

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San Diego, CA, United States of America

Stephen How