Creative Technology Corporation

Stephen Hoge

Eric W Lange

Thomas Craig Savell

An instruction set for control of an audio signal processor that allows for a high degree of flexibility in generating desired sound effects. The instruction set serves as a multi-functional instruction base upon which other specialized sound effects can be constructed.

Instruction set for controlling a processor to convert linear data to logarithmic data in a single instruction that define the exponent filed of the logarithmic value

A method for conserving memory storage during the execution of a interpolation operation uses a pool of interpolation commands. When a interpolation operation is requested, it is performed using one of the pooled interpolation commands. If none of the pooled interpolation commands are available, the interpolation command having the smallest difference between its interpolated value and final value is selected, and its interpolated value converted to its final value. The selected interpolation command is then reassigned to interpolate the requested data.

Method for conserving memory storage during an interpolation operation

A circuit for implementing digital delay lines that includes a main memory, a cache memory, and a processor. The main memory implements at least one digital delay line, as many delay lines as required by a digital signal processing (DSP) program running on the processor, up to a predetermined number. The delay lines contain data samples to be operated on, or produced by DSP program. The cache memory implements a number of delay caches that temporarily store data samples and support the delay lines. Each delay line is associated with a read cache and a write cache. A block of data samples are &ldquo;pre-fetched&rdquo; from a delay line in the main memory and provided to the associated read cache. The data samples in the read cache are then accessed, as needed, by the processor. Data samples generated by the DSP program are provided to the write cache. Periodically, a block of data samples is &ldquo;post-written&rdquo; from the write cache to its corresponding delay line in the main memory. The delay caches are serviced such that the read caches do not underflow and the write caches do not overflow, thereby effectively &ldquo;anticipating&rdquo; data accesses by the processor. In one embodiment of the delay line circuit, each of the delay lines includes a circular buffer. In another embodiment, each of the delay caches has a cache size that is greater than the data transfer size. In yet another embodiment, each delay cache is selected for servicing approximately once every servicing period, wherein the servicing period is approximately B sample periods or less and uses a servicing scheme such as a round robin scheme or a priority scheme.

Method and circuit for implementing digital delay lines using delay caches

A method and an system for communication between components of a computer system, such a plurality of computer soft-ware applications stored in a memory, that features uniquely associating each of the plurality of computer applications with a general purpose registers. Each of the general-purpose registers is in data communication with a common interrupt port of a processor via an interrupt control register and has a predetermined value associated therewith. A hardware interrupt is initiated by the interrupt control register in response to varying the predetermined value associated with one or more of the general purpose registers. In response to the interrupt, the processor polls each of the general purpose registers and initiates a callback function to the application associated with the general purpose register with the varied predetermined value. Although the predetermined value may consist of any number, typically the predetermined value is zero.

Interrupt control for multiple programs communicating with a common interrupt by associating programs to GP registers, defining interrupt register, polling GP registers, and invoking callback routine associated with defined interrupt register

A method for conserving processor registers during the execution of a program in which short term data having a short processing period and long term data having a long processing period are processed. The method includes the acts of: providing a program having a first address space for addressing the short term data and a second address space for addressing the long term data, defining within the processor a first plurality of pooled registers for storing the short term data, executing said program, allocating, responsive to the program, at least one of the pooled registers to the first address space, controlling, via said program, the allocated pool register for the duration of said short processing period, and terminating program control of the allocated pool register upon the expiration of said short processing period.

Method for conserving memory storage using a pool of short term memory

A memory initialization circuit for preventing random garbage data left over from a previous program from being read into a newly executed program. The initialization circuit is applicable to memories of all types, but is particularly useful for memories used to implement audio effects through the use of audio delay lines and audio tables. The memory initialization circuit includes multiple dual-use memory buffers, each of which store data for either a value representative of an audio delay length or an audio data signal. Multiple memory use indicators (e.g., flags) corresponding to the dual-use memory buffers indicate whether the data stored in each buffer represents an audio delay length or an audio data signal. The circuit also includes a counter that sequentially updates a count value and compare logic, which is coupled to the dual-use memory buffers and to the counter. The compare logic updates a given memory use indicator based on a comparison of the data stored in the memory buffer corresponding to the given memory use indicator and the value of the counter. When the counter reaches a stored audio delay length value, the memory use indicator is reset to a state that indicates valid TRAM data can be loaded into the memory buffer location. The circuit requires only one counter for the entire array of memory buffer locations.

Growing community of inventors

Santa Cruz, CA, United States of America

Stephen Hoge