Motorola Corporation

Stephen H Woltz

Walter L Davis

George A Drapac

Mark L Oliboni

In a selective call radio paging device, a plurality of alerts are generated in response to the decoding of a message having an address corresponding to the address assigned to the pager. A specific alert envelope waveform is generated and drives an alerting device of a first type (e.g., a transducer). Inverting means is provided to invert the envelope and cause a second alerting device (e.g., visual) to be activated in a manner complementary to the first. Thus, alerting devices are not operated concurrently, and peak loads on a resident power source are avoided.

Paging device with alternating alert outputs

A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.

Bit synchronizer

The pager receiver including a conventional address decoder, an alert envelope waveform generator, and an alert function mapper is disclosed. The pager is individually and uniquely characterized by programming the alert function mapper to govern the generation of assigned alert annunciation patterns by the waveform generator in response to selected decoded pager addresses and associated functions thereof, and to inhibit alert generation by the waveform generator in response to non-selected decoded pager addresses and associated functions thereof. In one embodiment, the alert signal waveform generator is enabled to respond to the alert function mapper only when the pager address is decoded by the decoder.

Programmable multi-address pager receiver and method of characterizing

A battery saving apparatus for supplying power to a selective call communication receiver for enabling the detection of a synchronization codeword in data received in a predetermined signaling format comprises circuits for supplying power to the receiver, and for detecting valid data received during a first portion of the first predetermined time interval. Power is maintained to the receiver for the remainder of the first predetermined time interval when valid data is detected in the first portion. A synchronization codeword detector is included for detecting a synchronization codeword. When valid data is subsequently detected following a second portion of the first predetermined time interval and the synchronization codeword is not detected in the first predetermined time interval, power is maintained to the receiver for a second predetermined time interval to further enable detection of the synchronization codeword.

Battery saving apparatus and method providing optimum synchronization

A power supply circuit includes a battery power source connected by a switch to the input of a DC to DC converter. The output of the DC to DC converter is connected to a filter capacitor and a load. A crow-bar is connected to the input and the output of the DC to DC converter. The crow-bar shorts the output to ground to discharge the capacitor when the voltage at the input drops to a predetermined value.

Filter capacitor discharge circuit for a DC-DC converter

An improved low-voltage, low-current, high-noise immunity I.sup.2 L interface is disclosed for control of associated I.sup.2 L logic circuitry, which interface does not require the inclusion of the heretofore conventional low-pass RC filter found in prior devices. As a result, considerable chip area previously occupied by such low-pass filters is now saved. Moreover, by isolating a portion of the interface switching circuitry from all other portions of the I.sup.2 L circuitry a substantial reduction in source current is effected. This objective is accomplished by fabricating at least one of the I.sup.2 L gates and its injector transistor in a separate epitaxial tub.

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Boca Raton, FL, United States of America

Stephen H Woltz