Intel Corporation

Other

Stephen H Gunther

Jeremy J Shrall

Robert J Greiner

Edward Allyn Burton

Avinash N Ananthakrishnan

Anant S Deval

Stephan Jourdan

Krishnakanth Venkata Sistla

Michael Cornaby

Sanjeev S Jahagirdar

Ankush Varma

Ryan Donovan Wells

Jay D Schwartz

Shaun M Conrad

Martin Rowland

Jason W Brandt

Bret L Toll

Varghese George

Alon Naveh

Inder M Sodhi

Efraim Rotem

Eliezer Weissmann

Devadatta V Bodas

Hung-Piao Ma

Xiuting C Man

Eugene Gorbatov

Stephen Anthony Fischer

Linda J Rankin

Eric J DeHaemer

Ian M Steiner

Anil Aggarwal

Matthew M Bace

Jack D Pippin

Chris Poirier

Elmoustapha Ould-Ahmed-Vall

Jesus Corbal

Martin Guy Dixon

Edward Thomas Grochowski

Per H Hammarlund

Scott Dion Rodgers

Prashant Sethi

Guy M Therien

Hang T Nguyen

David B Papworth

Eric DiStefano

Alan Beecher Kyker

Robert S Chappell

Michael N Derr

Douglas M Carmean

Frank Binns

Nicholas J Adams

Thomas R Huff

Daniel J Ragland

James D Allen

Buford M Guy

Vivek K De

Christopher J Hughes

David I Poisner

Eric C Samson

Keng L Wong

Matthew C Merten

Russell Jerome Fenger

Vivek Garg

Shivnandan D Kaushik

Lihu Rappoport

Sriram R Vangal

Vasudevan Srinivasan

Ronak Singhal

Jeffrey R Wilcox

Lance E Hacking

Tawfik M Rahal-Arabi

Roman Surgutchik

Robert Milstrey

Siva Ramakrishnan

Anupama Suryanarayanan

Ryan Carlson

Venkatesh Ramani

Randy B Osborne

James G Hermerding, Ii

Harish Krishnamurthy

Alexander Uan-Zo-Li

Willem M Beltman

Viktor D Vogman

Xia Dai

Ketan R Shah

Michael Zelikson

Alexander Lyakhov

Julien Sebot

Sameer Shekhar

Sapumal Wijeratne

Mark J Gallina

Brian J Griffith

Robert T Jackson

Tawfik Arabi

Borys S Senyk

Philip R Lehwalder

Jessica Gullbrand

Eugene P Matter

Arik Gihon

George Thangadurai

Described herein, in one embodiment, is a graphics processor comprising a plurality of dies integrated in a package, at least one die of the plurality of dies functionally heterogeneous relative to at least one other die of the plurality of dies and manufactured with a different process technology than the at least one other die.

Granular GPU DVFS with execution unit partial powerdown

A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.

Thermal management in horizontally or vertically stacked dies

An apparatus and method for temperature-constrained frequency control and scheduling. For example, one embodiment of a processor comprises: a plurality of cores; power management circuitry to control a frequency of each core of the plurality of cores based, at least in part, on a temperature associated with one or more cores of the plurality of cores, the power management circuitry comprising: a temperature limit-driven frequency controller to determine a first frequency limit value based on a temperature of a corresponding core reaching a first threshold; frequency prediction hardware logic to predict a temperature-constrained frequency of the corresponding core based on the first frequency limit value and an initial frequency limit value; and performance determination hardware logic to determine a new performance value for the corresponding core based on the temperature-constrained frequency, the new performance value to be provided to a task scheduler.

Apparatus and method for temperature-constrained frequency control and scheduling

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Apparatuses and methods for a processor architecture

A scheme for measuring AC and DC load-line (LL) using voltage and current monitoring apparatus. During calibration for LL measurement, a tested or known workload is executed on a processor or system-on-chip (SoC). The calibration can be done when the processor is first used in a real-time system (customer) scenario, or repeated whenever necessary to compensate silicon aging or other effects that affect the LL values. LL is estimated, determined, and/or calculated for each power supply rail in the processor or SoC. The measured LL is used in calculations that determine the operating voltage of an input voltage regulator (VR) at run time, thereby optimizing the power/performance characteristics of that specific system.

Per-part real-time load-line measurement apparatus and method

Systems, apparatuses and methods may provide for technology that automatically determines a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis. The technology may also automatically determine a runtime energy efficiency of the heterogeneous processing units, wherein the runtime energy efficiency is determined on a per efficiency class basis. In one example, technology selectively unparks one or more of the heterogeneous processing units based on the runtime performance and the runtime energy efficiency.

Hardware directed core parking based on performance and energy efficiency capabilities of processing units and runtime system characteristics

In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.

System, apparatus and method for sensor-driven and heuristic-based minimum energy point tracking in a processor

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Digital linear regulator clamping method and apparatus

An apparatus is provided, where the apparatus includes a plurality of processing cores to execute a plurality of processes, a register to store an indicator that is to indicate a preference for either performance or energy efficiency, a first circuitry to determine an effective utilization of a first processing core, based on the indicator, and a second circuitry to select at least one of an operating voltage or an operating frequency of the first processing core, based at least in part on the effective utilization of the first processing core.

Per-core operating voltage and/or operating frequency determination based on effective core utilization

According to one embodiment of the invention, a processor includes a power control unit, an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor, and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.

System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Independent power control of processing cores

Growing community of inventors

Beaverton, OR, United States of America

Stephen H Gunther