Zilog, Inc.

Maxim Integrated Products, Inc.

App Tsunami, Inc.

Stephen H Chan

Gyle Dee Yearsley

Boubekeur Benhamida

Grant B Richards

Edbert Chan

Jim Nobugaki

Website and newsletter operators may only have users' email addresses but not their person names. It can be beneficial for such operators to derive additional information about the email address owners so they can improve their services. However, there is no easy way to retrieve owners' information based on only email addresses. The present disclosure provides information such as the owners' names, professional profiles and aggregated statistics with only a list of email addresses as the input.

Method and system to analyze email addresses

A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Program memory space expansion for particular processor instructions

The present invention provides for data flow enhancement in processor architectures having one or more caches by allowing DMA-type transfers to and from these caches. Specific examples allow such direct transfers between a peripheral logic device and the cache memory, or between either the main memory or a special memory and the cache memory. This is done by the processor reserving a portion of cache for the direct transfer, which is then carried out by a DMA-type controller. While this transfer is occurring, the processor is able to carry out other tasks and access the unreserved portion of cache in the normal manner. In the preferred embodiment, the transfer is performed by a cycle stealing technique. Once the transfer is complete, the reserved portion of the cache may be accessed by the processor. The size of the reservable portion may either be fixed or dynamically determined by the operating system based on factors such as task flow management and data transfer rates. In a preferred embodiment, the operating system works in concert with the cache organized into cache lines, assigning each cache line an address tag field, with particular values of the address tag indicating that a given cache line is part of the reserved portion of the cache.

Data flow enhancement for processor architectures with cache

A flexible interrupt system for presenting interrupt signal to a microcontroller located on an integrated circuit responds to either on chip or off chip components. An interrupt circuit is connected to each bonding pad and is also connected to interrupt control logic which establishes priority for interrupt signals from the components located on chip. All interrupt signals pass through a common node in the interrupt circuit. A p channel transistor and a n channel transistor connected to the common node function as a pull up or pull down so that the microcontroller senses the rising or falling edge of the interrupt request. Since the interrupt request signals from either on chip components or off chip components pass through the common node, and the common node is directly coupled to a pad, system development and debug is simplified.

Flexible interrupt system for an integrated circuit

In a computer where instructions are fetched in segments and where segments of an instruction are assembled before execution is initiated, processing of instructions is accelerated by examining segments of the instructions they are fetched. The information obtained from such examination is then used to shorten the decoding step for the instruction.

Fast instruction decoding in a pipeline processor

Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.

Delayed FIFO status for serial shift emulation

In a computer where instructions are fetched in segments and where segments of an instruction are assembled before execution is initiated, processing of instructions is accelerated by examining segments of the instructions concurrently while they are being fetched. The information obtained from such examination is then used to shorten the decoding step for the instruction.

Technique for accelerating instruction decoding of instruction sets with

A new technique for testing the counting functionality, loading functionality, and operational speed of a binary counter is provided wherein additional logic is incorporated into the counter to enable the counter to be functionally tested with a minimum number of clock cycles. Thus, for an n-bit counter which is partitionable into k subcounters, the counting functionality and operational speed of the counter may be tested in at most 2.sup.n/k +2 clock cycles, and the loading functionality of the counter may be tested in at most 2.sup.n/k +1 clock cycles.

Efficient functional test scheme incorporated in a programmable duration

A method and apparatus for using multiple program counters to reduce the latency time of a computer in response to an interrupt or subroutine call using a memory with multiple memory locations for storing the multiple program counters and control means in order to choose which one of the memory locations is used as a current program counter. Additionally, the use of a memory location to store the starting address of the interrupt subroutine is also disclosed.

Minimal interrupt latency scheme using multiple program counters

An electronic circuit employed in a microprocessor system inserts a programmable number of wait states in a machine cycle of the microprocessor in response to a specific operational code of the microprocessor's instruction set being detected on a system data bus. A particular application of the wait state generation circuit is to provide enough time for a control signal to propagate along a plurality of daisy-chained peripherals before the microprocessor machine cycle ends. The wait state generation circuit may be provided as part of the microprocessor on a single integrated circuit chip.

Programmable wait states generator for a microprocessor and computer

A circuit for transferring data from one bus system to another is disclosed. The circuit allows the write bus to perform write operations indiscriminately of any handshaking, wait states or other control signals which would otherwise reduce the bus efficiency of the system. Similarly, the read bus system has no handshaking or wait states but is provided with a data ready signal to indicate when valid data may be read. This circuit is used in applications where less than 100% data integrity is permissible.

Growing community of inventors

Sunnyvale, CA, United States of America

Stephen H Chan