Motorola Corporation

Stephen G Oller

Robert W Deutsch

Dean M Picha

John H Aseltine

David J Wagner

Daniel D Prochaska, Sr

Robert J Laping

Diagnostic fault test system and circuit sequentially tests a plurality of drivers (12) and their associated solenoid loads (13). Control signals (PM, SM) are provided to the drivers by a computer controller (11) to achieve desired solenoid actuation. The controller temporarily alters the control signals such that all of the drivers are forced into an on or off state for a first time period (t.sub.A or t.sub.B). After a delay (t.sub.Don or t.sub.Doff) a signal (V.sub.M) associated with each driver stage is monitored to determine if the driver and its load are operating properly. Then the controller resumes normal control of the drivers. The duration of the forced on/off state is short enough so as not to cause a change in the actuated/nonactuated state of the solenoid loads. Each monitored signal from the driver is sequentially compared to a high and low threshold (50, 51) to indicate either proper operation or the identification of one of two different types of fault which may occur. Drivers are preferably tested in both on and off states for proper operation and identification of a total of four different possible faults. Present system allows rapid testing of all drivers and their loads by use of a common transient setting delay time. Accuracy is improved since driver switching during fault monitoring is not permitted. Fewer components are needed since a single comparator (18) is used to sequentially compare each monitored signal for each driver with both high and low thresholds. Also, an indication of what type of fault is provided rather than just providing an indication that some fault exists.

Diagnostic fault test system and circuit

A main microprocessor A (11) provides data to a display formatter microprocessor B (12) via a data bus (13). Microprocessor B provides data and latch (activity) pulses (34A) to a visual display (27) comprising a number of individual display devices (28-30) which are sequentially excited by data obtained from microprocessor B. An external activity detector (38), in response to an absence of the latch pulses of microprocessor B for a predetermined time, generates a reset signal (40) for resetting the microprocessor A. In response to being reset, microprocessor A provides an output control signal (at 20) which results in the resetting of the microprocessor B. If microprocessor B determines that microprocessor A is not properly providing data to it, microprocessor B will terminate generating the latch pulses (34A). The preceding configuration results in each of the microprocessors effectively monitoring the operation of the other microprocessor so as to insure proper system operation. Therefore, this system properly resets itself in response to any of a large number of different failures which may occur in either of the microprocessors, and this is accomplished with a minimum of additional hardware circuitry and software programming.

Multiple microprocessor watchdog system

Growing community of inventors

Schaumburg, IL, United States of America

Stephen G Oller