Apple Inc.

Stephen G Meier

Tyler J Huberty

Eric Jason Furbish

Sandeep Kumar Gupta

Andrew J Beaumont-Smith

John D Pape

Vivek Venkatraman

Brandon H Dwiel

Mridul Agarwal

Srinivasa Rangan Sridharan

Peter G Soderquist

Chandan Shantharaj

Yanran Yang

Sahil Kapoor

An apparatus includes a cache memory circuit, a prefetcher circuit, and a prefetch deny list circuit, including a plurality of entries, may be included. The cache memory circuit may be configured to store information retrieved from a lower-level memory. The prefetcher circuit may be configured to generate a prefetch request for a particular prefetch address. The prefetch deny list circuit may be configured to allocate, in response to an indication from the cache memory circuit that a previously prefetched address went unused, a given entry, of the plurality of entries, for the previously prefetched address. The prefetch deny list circuit may be further configured to determine whether a particular address for a particular prefetch request corresponds to an active one of the plurality of entries. In response to a determination that a particular active entry corresponds to the particular address, prefetch deny list circuit may deny the particular prefetch request.

Deny list for a memory prefetcher circuit

A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates. Multiple levels of criticality may be available for a given cache line and cache circuitry may adjust the criticality value of in response to a criticality event. One or more upper criticality levels may be masked when selecting a victim cache line for replacement.

Criticality-informed caching policies with multiple criticality levels

A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

Coprocessor prefetcher

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Los Altos, CA, United States of America

Stephen G Meier