Hewlett-packard Development Company, L.P.

Hewlett Packard Enterprise Development LP

Trend Micro Inc.

Tandem Computers Incorporated

Compaq Computer Corporation, Inc.

Stephen G Low

Michael S Schlansker

David J Garcia

William J Watson

Robert W Horst

Jean Tourrilhes

William P Bunton

Paul Allen Bottorff

John C Krause

Charles L Hudson

David P Sonnier

James Michael Rolette, Jr

William Edward Baker

Richard W Cutts, Jr

Matthew Laswell

Linda Ellen Zalzala

John Michael Brown

John D Coddington

Dwight L Barron

Paul T Congdon

William F Bruckert

Jose Renato G Santos

Douglas E Jewett

Susan S Meredith

Steven C Meyers

Geoffrey I Iswandhi

Richard O Larson

Daniel L Fowler

Patricia L Whiteside

Frank A Williams

Randall G Banton

Paul N Hintikka

James Stevens Klecka

Edward A Wartha

Gary F Campbell

Curtis Willard Jones, Jr

Mark A Pearson

Barry Lee Drexler

Harry Frank Elrod

Patracia L Whiteside

According to an example, configurable workload optimization may include selecting a performance optimized application workload from available performance optimized application workloads. A predetermined combination of removable workload optimized modules may be selected to implement the selected performance optimized application workload. Different combinations of the removable workload optimized modules may be usable to implement different ones of the available performance optimized application workloads. The predetermined combination of the removable workload optimized modules may be managed to implement the selected performance optimized application workload. Data flows directed to the predetermined combination of the removable workload optimized modules may be received. The data flows may be analyzed based on attributes of the data flows, and redirected for processing by one of the removable workload optimized modules of the predetermined combination of the removable workload optimized modules based on the analysis.

Combinations of removable workload optimized modules for implementing different application workloads

According to an example, configurable network security may include receiving data flows directed to end node modules of a server, and selecting data flows from the received data flows based on an analysis of attributes of the received data flows. The selected data flows may be less than the received data flows. A number of IPS data plane modules of the server that are available for inspection of the selected data flows may be determined. The selected data flows may be distributed between the IPS data plane modules based on the determined number of the IPS data plane modules. The distributed data flows may be inspected using the IPS data plane modules to identify malicious and benign data flows, and to determine whether to drop the malicious data flows, direct the malicious data flows to a predetermined destination, or forward the benign data flows to the end node modules.

Configurable network security

Embodiments of the present disclosure may include methods, systems, and computer readable media with executable instructions. An example method for network virtualization can include providing, by a datacenter () having physical and/or virtual resources, a number of virtual tenant datacenters (tDatacenters), each tDatacenter being isolated from other tDatacenters. A tenant virtual local area network (T-VLAN) () is associated to each of the number of tDatacenters, and a value of an end-to-end invariant network virtual local area network (VLAN) identification (VID) label (T-VID) is associated to a particular T-VLAN (). A network packet associated with the particular T-VLAN () is modified at an edge network boundary () to include the T-VID. The T-VID is configured to have more than 4096 possible values.

Network virtualization

One example provides a network device including a queue to receive frames from a source, a processor, and a memory communicatively coupled to the processor. The memory stores instructions causing the processor, after execution of the instructions by the processor, to determine whether a flow control threshold of the queue has been exceeded, and in response to determining that the flow control threshold of the queue has been exceeded, generate a message to be sent to the source of the frame that exceeded the flow control threshold. The message includes a pause duration for which the source is to stop transmitting frames.

Flow control in a network

A system and method are provided to route packets in a data center network. Individual packets are encapsulated at an edge of the data center network, so that each encapsulated packet includes a set of header fields, such as a tenant identifier. For each encapsulated packet, a hash class is determined from the set of header fields. A routing virtual local area network (VLAN) is selected for the packet based on the tenant identifier and the hash class.

Routing encapsulated data packets onto selected VLANs

According to one example of the present invention, there is provided a method of routing data packets to a plurality of packet processors in a computer network. The method comprising obtaining workload data from the packet processors, determining a workload distribution across the packet processors, and updating a balancing table used by a switching element in the network based on the determined workload.

Data packet routing

A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes, coupled by a plurality of paths, that maintain the good and bad status of each path and also maintain local copies of a message sequence number. If an error occurs for a transaction over a given path, the requestor informs the responder, over a good path, that the given path has failed and both nodes update their path status to indicate that the given path is bad. A barrier transaction is used by the requestor to determine whether the error is transient or permanent, and, if the error is transient, the requestor retries the transaction.

System and method for implementing error detection and recovery in a system area network

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Method of data communication flow control in a data processing system

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

Growing community of inventors

Austin, TX, United States of America

Stephen G Low