Motorola Corporation

Stephen G Jamison

Percy V Gilbert

Paul G Tsui

Edward Outlaw Travis, Jr

Jeremy Charles Smith

Shih-Wei Sun

Ting-Chen Hsu

Clifford M Howard

James W Miller

A segmented bus architecture (800) removes certain ESD circuitry from each I/O pad cell (806, 812) and places it in a power pad cell (808, 814) or in some other unused area of the integrated circuit which incorporates the SBA. The removed ESD circuit is shared by several adjacent I/O pad cells via a segmented ESD bus. As a result, each individual I/O pad cell may be reduced in size.

Segmented bus architecture (SBA) for electrostatic discharge (ESD)

An electrostatic discharge (ESD) circuit (700) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a bipolar transistor (202). The bipolar device is triggered by a combination of an n-type MOSFET (702), a string of diodes (200), and a biasing circuit (704). The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. The relatively high transconductance of the n-type MOSFET allows the use of a smaller ESD circuit for a given degree of protection.

Circuit for electrostatic discharge (ESD) protection

Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.

Semiconductor device having a bond pad

An SOI structure (20) includes a semiconductor layer (15) formed on an insulating substrate (12). The semiconductor layer (15) is partitioned into an ESD protection portion (32) and a circuitry portion (34). A portion of the semiconductor layer (15) in the ESD protection portion (32) and a different portion of the semiconductor layer (15) in the circuitry portion (34) are differentially thinned. A device (60) which implements the desired circuit functions of the SOI structure (20) is fabricated in the circuitry portion (34). An ESD protection device (40) is fabricated in the ESD protection portion (32). The thick semiconductor layer (15) in the ESD protection portion (32) serves to distribute the ESD current and heat over a large area, thereby improving the ability of the SOI structure (20) to withstand an ESD event.

Method of making an SOI integrated circuit with ESD protection

A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.

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Buda, TX, United States of America

Stephen G Jamison