The Dow Chemical Company

Dow Global Technolgoies LLC

Stephen G Churchill

Wayne P Dupree

Larry A Root

Srikala Ramaswamy

David M Jachim

William J Bressette

Jeffrey A Lucas

Gerrit H Verniers

Robert A Orr, Iii

Jeffry R Gallant

Randy D Woods

George P Fernandez

James A Bleck

A system is presented for a plurality of computer nodes in mutual data communication to execute logic in a coordinated manner. The approach features aligning the definition of the time in the nodes so that each node has essentially the same definition of time; defining a schedule of communications for each computer node, with the schedule having future moments defined for initiating each communication; communicating each schedule to its respective node; and initiating each communication at the time defined in the schedule. The computer network has a message carrier supporting multiple communication paths; a plurality of computers coupled to the message carrier, a clock system for maintaining time synchronism among the computers; and a scheduler coupled to the message carrier for determining the sequence of communication between the computers. The message carrier establishes communication between selected computers based on the time-deterministic tasks being performed by the computers. A computer node in the plurality of computer nodes executes logic in coordination with the other nodes by defining a communication request list of each communication needed by the computer node with any other computer node respective to a future time period, sending the communication request list to the master scheduler, receiving back a communication schedule back from the master scheduler, defining a local task schedule from the communication schedule, and then executing the communication at the scheduled time.

Distributed computing environment using real-time scheduling logic and time deterministic architecture

A massively multiplexed central processing unit ('CPU') which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus. The CPU also features a very long instruction word which uses a series of assigned bit locations to represent the selections codes for each of the CPU components. These selection codes are directly transmitted to each of the CPU components by a program control circuit. A separate data control circuit is further provided in achieve a Harvard architecture design for the CPU.

Massively multiplexed superscalar Harvard architecture computer

Growing community of inventors

Midland, MI, United States of America

Stephen G Churchill